74LVC1G126GV

The 74LVC1G126 is a single-bus buffer/line driver with 3-state output. Its inputs can be driven by 3.3 V or 5 V devices. This feature allows the device to be used as a level translator in mixed 3.3 V and 5 V environments. All inputs incorporate Schmitt-trigger action, making the circuit tolerant of slower input rise and fall times. The device is fully specified for partial-power-down applications using the IOFF feature. The IOFF circuitry disables the output when the device is powered down, preventing potential damage due to reverse current flowing through the device.

Key features

• Wide supply voltage range: 1.65 V ~ 5.5 V
• Input overvoltage tolerance up to 5.5 V
• High noise immunity
• CMOS low power consumption
• IOFF circuitry for partial power-down mode operation
• ±24 mA output drive capability (VCC = 3.0 V)
• Latch-up performance exceeds 100 mA
• Direct TTL-level interface compatible
• JEDEC compliant: JESD8-7 (1.65 V ~ 1.95 V), JESD8-5 (2.3 V ~ 2.7 V), JESD8C (2.7 V ~ 3.6 V), JESD36 (4.5 V ~ 5.5 V)
• ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V, MM JESD22-A115C Class C exceeds 550 V, CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
• Multiple package options