ADCLK846BCPZ-REEL7

The ADCLK846 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low-jitter, low-power applications. It is configurable from 6 LVDS to 12 CMOS outputs, including combinations of LVDS and CMOS outputs. Two control lines are used to select either LVDS or CMOS outputs as fixed outputs. Various single-ended and differential logic levels, including LVPECL, LVDS, HSTL, CML, and CMOS, are accepted as clock inputs. The SLEEP pin enables sleep mode to power down the device. The device is available in a 24-lead LFCSP package. It is rated for operation over the -40°C to +85°C temperature range (standard industrial temperature range).

Applications

• Low-jitter clock distribution
• Clock and data signal recovery
• Level translation
• Wireless communications
• Wired communications
• Medical and industrial imaging
• ATE and high-performance instrumentation

Key features

• Selectable LVDS/CMOS outputs
• Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs
• Per-channel power < 16 mW (at 100 MHz operating frequency)
• Integrated jitter: 54 fs (12 kHz to 20 MHz)
• Additive wideband jitter: 100 fs
• Propagation delay: 2.0 ns (LVDS)
• Output rise/fall time: 135 ps (LVDS)
• Output-to-output skew: 65 ps (LVDS)
• Sleep mode
• Pin-programmable control
• Supply voltage: 1.8 V