AM4378BZDND100

TI AM437x high-performance processors are based on the ARM Cortex-A9 core. These processors are enhanced with 3D graphics acceleration to enable rich graphical user interfaces. They are also equipped with coprocessors for deterministic real-time processing (including industrial communication protocols such as EtherCAT, PROFIBUS, and EnDat). The device supports high-level operating systems (HLOS). Linux-based HLOS can be obtained from TI for free. Other HLOS can be obtained from TI's design network and ecosystem partners. These devices support the upgrade of systems using lower-performance ARM cores and offer newer peripherals, including memory options such as QSPI-NOR and LPDDR2. The processor subsystem is based on the ARM Cortex-A9 core. The PowerVR SGX graphics accelerator subsystem provides 3D graphics acceleration to support displays and advanced user interfaces. The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) are separate from the ARM core, allowing for independent operation and timing to achieve higher efficiency and flexibility. The PRU-ICSS supports more peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and EnDat. The PRU-ICSS can support EnDat and another industrial communication protocol in parallel. In addition, thanks to the programmable nature of the PRU-ICSS and its access to pins, events, and all System-on-Chip (SoC) resources, this subsystem can flexibly achieve fast real-time responses, dedicated data processing operations, and customized peripheral interfaces, and flexibly offload the task load from other processor cores of the SoC. The high-performance interconnect provides high-bandwidth data transfer for multiple boot programs to internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock management mechanism. An on-chip analog-to-digital converter (ADC0) can be combined with the display subsystem to provide an integrated touchscreen solution. Another ADC (ADC1) can be combined with the pulse width module to create a closed-loop motor control solution. The RTC provides a clock reference in an independent power domain. This clock reference enables a battery-powered clock reference. The camera interface provides configurations suitable for single-camera or dual-camera parallel ports. Each AM437x device has encryption acceleration capabilities. Only the AM437xHS devices have a secure boot function for anti-cloning and protection against unauthorized software updates.

Applications

• Patient monitoring
• Navigation equipment
• Industrial automation
• Portable data terminals
• Barcode scanners
• Point of sale
• Portable mobile radio
• Test and measurement

Key features

• Sitara ARM Cortex-A9 32-bit RISC processor up to 1000MHz
• NEON SIMD coprocessor and VFPv3 coprocessor
• 32KB L1 instruction and data cache
• 256KB L2 cache or L3 RAM
• 32-bit LPDDR2, DDR3, and DDR3L support
• General-purpose memory support (NAND, NOR, SRAM) with up to 16-bit ECC
• SGX530 graphics engine
• Display subsystem
• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
• RTC
• Up to two USB 2.0 high-speed dual-role (host or device) ports with integrated PHY
• Up to 2-port 10/100/1000 Ethernet switch
• Serial interfaces:
• Two CAN ports
• Six UARTs, two McASPs, five McSPIs, three I2C ports, one QSPI, and one HDQ or 1-Wire
• Security:
• Cryptographic hardware accelerators (AES, SHA, RNG, DES, and 3DES)
• Secure boot (available only on AM437x High Security [AM437xHS] devices)
• Two 12-bit SAR ADCs
• Up to three 32-bit eCAP modules
• Up to three eQEP modules
• Up to six eHRPWM modules
• MPU subsystem:
• ARM Cortex-A9 32-bit RISC microprocessor up to 1000MHz
• 32KB L1 instruction and data cache
• 256KB L2 cache (also configurable as L3 RAM)
• 256KB on-chip boot ROM
• 64KB on-chip RAM
• Secure Control Module (SCM) (available only on AM437xHS devices)
• Emulation and debug:
• JTAG
• Embedded trace buffer
• Interrupt controller
• On-chip memory (shared L3 RAM):
• 256KB General-Purpose On-Chip Memory Controller (OCMC) RAM
• Accessible by all masters
• Retention support for fast wakeup
• Up to 512KB total internal RAM (256KB ARM memory configured as L3 RAM + 256KB OCMC RAM)
• External Memory Interface (EMIF):
• DDR controller:
• LPDDR2: 266MHz clock (LPDDR2-533 data rate)
• DDR3 and DDR3L: 400MHz clock (DDR-800 data rate)
• 32-bit data bus
• 2GB fully addressable space
• Supports one x32, two x16, or four x8 memory device configurations
• General-Purpose Memory Controller (GPMC):
• Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, and SRAM)
• 4-bit, 8-bit, or 16-bit ECC using BCH codes
• 1-bit ECC using Hamming code
• Error Location Module (ELM):
• Works with GPMC to locate addresses of data errors from companion polynomials (generated when using BCH algorithm)
• 4-bit, 8-bit, and 16-bit error location per 512-byte block based on BCH algorithm
• PRU-ICSS:
• Supported protocols include EtherCAT, PROFIBUS, PROFINET, EtherNet/IP, EnDat 2.2, etc.
• Two PRU subsystems, each with two PRU cores
• Each core is a 32-bit load/store RISC processor running at 200MHz
• 12KB (PRU-ICSS1) / 4KB (PRU-ICSS0) instruction RAM with single-error detection (parity)
• 8KB (PRU-ICSS1) / 4KB (PRU-ICSS0) data RAM with single-error detection (parity)
• Single-cycle 32-bit multiplier with 64-bit accumulator
• Enhanced GPIO module with shift-in/shift-out and parallel latch support for external signals
• 12KB shared RAM with single-error detection (parity) (PRU-ICSS1 only)
• Three 120-byte register banks accessible by each PRU
• INTC for handling system input events
• Local interconnect bus for connecting internal and external masters to PRU-ICSS internal resources
• Peripherals within PRU-ICSS:
• One UART port with flow control pins, supporting data rates up to 12Mbps
• One eCAP module
• Two MII Ethernet ports supporting industrial Ethernet (e.g., EtherCAT)
• One MDIO port
• Two PRU-ICSS subsystems supporting industrial communication
• Power, Reset, and Clock Management (PRCM) module:
• Controls entry and exit of deep sleep mode, handling sleep sequencing, power domain shutdown sequencing, wakeup sequencing, and power domain power-on sequencing
• Clocks:
• Integrated high-frequency oscillator for generating reference clocks for various system and peripheral clocks (19.2, 24, 25, and 26MHz)
• Individual clock enable/disable control for subsystems and peripherals for reduced power consumption
• Five ADPLLs for generating system clocks (MPU subsystem, DDR interface, USB and peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], and LCD pixel clock)
• Power:
• Two non-switchable power domains (RTC and wake-up logic [WAKE-UP])
• Three switchable power domains (MPU subsystem, SGX530 [GFX], and peripherals and infrastructure [PER])
• Dynamic Voltage and Frequency Scaling (DVFS)
• RTC:
• Real-time date (year, month, day, and day of week) and time (hours, minutes, and seconds)
• Internal 32.768kHz oscillator, RTC logic, and 1.1V internal LDO
• Dedicated power-on reset (RTC_PWRONRSTn) input
• Dedicated external wakeup event input pin (RTC_WAKEUP)
• Programmable alarm generating PRCM internal interrupt for wakeup or Cortex-A9 internal interrupt for event notification
• Programmable alarm usable with external output (RTC_PMIC_EN) to enable PMIC for restoring non-RTC power domains