AT32F425C8T7

Based on ARM 32-bit Cortex-M4 microcontroller, with 32 KB to 64 KB flash, sLib, 1x CAN, 1x OTG FS, 13x timers, 1x ADC, 12x communication interfaces

Key features

• Core: ARM 32-bit Cortex-M4 CPU, up to 96 MHz operating frequency, with MPU, single-cycle multiplication and hardware division, DSP instruction set
• Memory: 32 KB to 64 KB flash memory; 4 KB boot code area for Bootloader, one-time configurable as general user area; sLib designates specified main memory region as secure execution code library — code in this region is callable but not readable; 20 KB SRAM
• Power Control (PWC): 2.4V to 3.6V supply; POR, LVR, PVM; low-power modes: Sleep, Deep Sleep, and Standby, with 6 WKUP pins to wake from Standby; 5 battery-powered 32-bit backup registers (BPR)
• Clock and Reset Management (CRM): 4 to 25 MHz crystal oscillator (HEXT); factory-trimmed 48 MHz HICK, ±1% accuracy at 25℃, ±0.2% accuracy over -40℃ to +105℃, with ACC; flexible PLL multiplication and division configuration; 32 kHz crystal (LEXT); LICK
• Analog: 1× 12-bit 2 MSPS ADC, up to 16 external input channels; hardware oversampling up to 16-bit resolution; internal reference voltage (VINTRV)
• DMA: 1× DMA controller, full flexible mapping, 7 channels
• Up to 55 fast GPIO ports: all GPIOs mappable to 16 EXINTs; almost all GPIOs 5V-tolerant
• Up to 13 timers (TMR): 1× 16-bit 7-channel advanced timer with 6-channel PWM output, dead-time control, and emergency stop; up to 6× 16-bit and 1× 32-bit general-purpose timers, each with up to 4 channels for input capture/output compare/PWM or pulse counting, and incremental encoder input; up to 24 PWM channels combined across advanced and general-purpose timers; 2× 16-bit basic timers; 2× watchdog timers (WDT and WWDT); SysTick 24-bit down counter
• ERTC: enhanced RTC with auto-wakeup, alarm, sub-second precision, hardware calendar, and calibration
• Up to 12 communication interfaces: 2× I2C, SMBus/PMBus support; 4× USART with master synchronous SPI and modem control, ISO7816, LIN, IrDA, RS485 driver enable, and configurable TX/RX pin swap; 3× SPI (36 Mbit/s), each remappable as half-duplex I2S, any 2 half-duplex I2S combinable into 1 full-duplex I2S; CAN (2.0B Active) with dedicated 256-byte SRAM; OTG full-speed controller with dedicated 1280-byte SRAM, Crystal-less support in device mode; IRTMR
• CRC calculation unit; 96-bit unique chip ID (UID)
• Debug: SWD and SWO interfaces
• Temperature range: -40℃ to +105℃