AT89C51CC01UA-SLSUM

- After a write of more than 32 bytes in the EEPROM and 16 bytes in the user Flash memory, the read of the first byte may be disturbed if it occurs just after the write. - Large bounces and high noise are generated when buffers are switching (both rising and falling edges). - When the CPU is in X2 mode and Timer 1 or Timer 0 in X1 mode Γ(CKCON = 0x7F), IEx flag is not cleared by hardware after servicing interrupt. In this case, the CPU executes the ISR a second time. - No movc instruction is performed when a program running on the boot memory tries to read its own code using a movc instruction. - Power OFF Flag does not work. - When a stuff error occurs during a CAN frame transmission on DPRAM write access, the controller does not generate the error interrupt and any received frame can generate a Receive interrupt. - In baud rate generator mode, setting TF2 by software does not generate an interrupt. - When Timer 2 is used as a baud rate generator, TH2 is not loaded with RCAP2H at the beginning, then UART is not operational before 10000 machine cycles. - May lose RB8 value, if RB8 changes from 1 to 0 during JBC instruction on SCON register. - The problem occurs during an A/D conversion in idle mode. If a hardware interrupt occurs followed by a second interrupt with higher priority before the end of the A/D conversion. If the above configuration occurs, the highest priority interrupt is served immediately after the A/D conversion. At the end of the highest priority interrupt service, the processor will not serve the hardware reset interrupt pending. It will also not serve any new interrupt requests with a priority lower than the high level priority last served. - When the stuff error occurs (same condition than the errata 6), the CONCH1, CONCH0 bits in CANCONCH are corrupted. This corruption has no effect on the behavior of the Transmit channel. - In the ‘In - Application Programming’ mode from the Flash, if the User software application loads the Column Latch Area prior to calling the programming sequence in the CAN Bootloader, the ‘after load’ issue leads to a wrong Opcode Fetch during the column latch load sequence. - When BRP = 0 or when BRP > 0 and SMP = 0, the CAN controller may desynchronize and send one error frame to ask for the retransmission of the incoming frame, even though it had no error. This is likely to occur with BRP = 0 or after long inter - frame periods without synchronization (low bus load). The CAN macro can still properly synchronize on frames following the error. - When exiting power - down mode by interrupt while CPU is in X2 mode, it leads to bad execution of the first instruction run when CPU restarts. - When the Timer0 is in X1 mode and Timer1 in X2 mode and vice versa, extra... (text seems incomplete here)