ATMEGA64A-AU

The ATmega64A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64A achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega64A provides the following features: 64 Kbytes In-System Programmable Flash with Read-WhileWrite capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run. The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot Program can use any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega64A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega64A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.

Key features

• High-performance, Low-power Atmel AVR 8-bit Microcontroller
• Advanced RISC Architecture
• 130 Powerful Instructions
• Most Single Clock Cycle Execution
• 32x8 General Purpose Working Registers + Peripheral Control Registers
• Fully Static Operation
• Up to 16 MIPS Throughput at 16 MHz
• On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
• 64 Kbytes of In-System Reprogrammable Flash program memory
• 2 Kbytes EEPROM
• 4 Kbytes Internal SRAM
• Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
• Data retention: 20 years at 85℃/100 years at 25℃
• Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
• Up to 64 Kbytes Optional External Memory Space
• Programming Lock for Software Security
• SPI Interface for In-System Programming
• JTAG (IEEE std. 1149.1 Compliant) Interface
• Boundary-scan Capabilities According to the JTAG Standard
• Extensive On-chip Debug Support
• Programming Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
• Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
• Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode
• Real Time Counter with Separate Oscillator
• Two 8-bit PWM Channels
• 6 PWM Channels with Programmable Resolution from 1 to 16 Bits
• 8-channel, 10-bit ADC
• 8 Single-ended Channels
• 7 Differential Channels
• 2 Differential Channels with Programmable Gain (1x, 10x, 200x)
• Byte-oriented Two-wire Serial Interface
• Dual Programmable Serial USARTs
• Master/Slave SPI Serial Interface
• Programmable Watchdog Timer with On-chip Oscillator
• On-chip Analog Comparator
• Special Microcontroller Features
• Power-on Reset and Programmable Brown-out Detection
• Internal Calibrated RC Oscillator
• External and Internal Interrupt Sources
• Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby
• Software Selectable Clock Frequency
• ATmega103 Compatibility Mode Selected by a Fuse
• Global Pull-up Disable
• I/O and Packages
• 53 Programmable I/O Lines
• 64-lead TQFP and 64-pad QFN/MLF
• Operating Voltages
• 2.7 - 5.5V for ATmega64A
• Speed Grades
• 0 - 16 MHz for ATmega64A