CH543D

CH543 is a USB and USB PD enhanced E8051 core MCU compatible with the MCS51 instruction set, with 79% of its instructions being single-byte single-cycle instructions, delivering an average instruction speed 8~15 times faster than standard MCS51. CH543 integrates 16K program Flash-ROM, 256-byte internal iRAM, and 256-byte on-chip xRAM, with xRAM supporting DMA direct memory access. CH543 features a built-in USB Power Delivery controller and PD BMC PHY transceiver, supporting USB Type-C, BC, PD2.0, and PD3.0, with 12V high-voltage power supply support, functioning as a PMIC for power management, power sink, power source, and DRP applications. CH543 integrates a USB host controller and transceiver, supporting full-speed and low-speed USB Host and USB Device. CH543 also incorporates a 12-bit ADC, capacitive touch key detection module, internal oscillator, 3 timer groups with 2-channel signal capture, 4-channel PWM, UART, SPI, I2C slave, and programmable current sink module. CH541 is a USB MCU supporting 12V power supply. Based on CH543, CH541 removes the USB PD, USB host, and programmable current sink module while retaining the Type-C module; all other features are identical to CH543. Refer to the CH543 manual and documentation for details.

Key features

• Core: Enhanced E8051 core, MCS51 instruction set compatible; 79% of instructions are single-byte single-cycle, average instruction speed 8~15× faster than standard MCS51; dedicated XRAM fast data copy instruction, dual DPTR pointers.
• ROM: 16KB non-volatile Flash-ROM, supports 10K erase/write cycles; fully usable as program storage, or partitioned into 14KB program area, 256B EEPROM data area, and 1.75KB BootLoader/ISP code area.
• EEPROM: 256-byte data EEPROM, divided into 4 independent blocks; supports single-byte read, single-byte write, block write (⇌64 bytes), block erase (64 bytes); typically supports 100K erase/write cycles under normal conditions.
• OTP: 32-byte one-time programmable data area; supports double-word read (4 bytes) and single-byte write.
• RAM: 256-byte internal iRAM for fast data buffering and stack; 256-byte on-chip xRAM for data buffering and USB/USB PD DMA access.
• USB: Integrated USB controller and USB transceiver; supports USB-Host and USB-Device modes; USB 2.0 full-speed 12Mbps or low-speed 1.5Mbps; max 64-byte packet size; built-in FIFO; DMA support; BC charging protocol support; UART async RXD/TXD pin mapping support.
• USB PD and Type-C: Integrated USB Power Delivery controller and PD transceiver PHY; USB Type-C DRP/host/device detection; automatic BMC encoding/decoding and CRC; hardware edge control; DMA support; USB PD2.0 and PD3.0 power delivery control; DRP support.
• Timer: 3× 16-bit timers; T0/T1/T2 are standard MCS51-compatible timers.
• Capture: Timer T2 extended to support 2-channel signal capture; rising edge, falling edge, and period detection.
• PWM: 4-channel 8-bit standard PWM output or 2-channel high-precision 12-bit PWM output; interleaved output support.
• UART: Standard MCS51 async serial port; up to 3Mbps or 460800bps baud rate.
• SPI: Master/Slave mode; built-in FIFO; clock frequency up to nearly half of system clock Fsys; serial data I/O simplex multiplexing support.
• I2CS: I2C slave controller; supports 1MHz clock.
• ISINK: 512-level programmable current sink, equivalent to 9-bit DAC; PPS support.
• ADC: 12-channel 12-bit ADC; selectable input buffer or simple amplification.
• Touch-Key: 11-channel capacitive touch key detection; every ADC channel except RST supports touch key detection.
• GPIO: Up to 17 GPIO pins (including USB, USB PD, and RST pins); MCS51-compatible quasi-bidirectional mode; additional high-impedance input, push-pull output, and open-drain output modes.
• P3.5 pin supports VDD12 high-voltage 12V I/O; RST pin as general-purpose input supports VDD12 high-voltage 12V.
• Interrupt: 14 interrupt sources; includes 6 MCS51-compatible interrupts (INT0, T0, INT1, T1, UART0, T2) and 8 extended interrupts (SPI0, I2C, USB, ADC, USB PD, PWMX/CMP, GPIO, WDOG); GPIO interrupt selectable from multiple pins.
• Watch-Dog: 8-bit presettable watchdog timer WDOG; timed interrupt support.
• Reset: 7 reset sources; built-in POR, LVR, and OVR modules; software reset and watchdog overflow reset; optional external pin reset; optional USB PD hardware reset.
• Clock: Built-in 48MHz clock source for generating system clock Fsys and USB clock.
• Power: Built-in 12V to 3.3V or 4.7V LDO regulator for USB, I/O, ADC, and other modules; VDD12 supports 5V, 3.3V, 9V, 12V, or 2.8V supply voltage.
• VDD12 high-voltage discharge and RST pin 12V high-voltage discharge support.
• Sleep: Low-power sleep mode; wake-up via USB, USB PD/Type-C, UART0, SPI0, and selected GPIO pins.
• Unique on-chip ID with ID readback and verification support.
• Available in compact QFN and cost-effective SOP16 packages.