CH591D

CH592 is a RISC-V MCU microcontroller with integrated BLE wireless communication. On-chip integration of 2Mbps BLE communication module, full-speed USB host and device controller and transceiver, segment LCD driver module, SPI, 4 serial ports, 12-channel ADC, touch-key detection module and other rich peripheral resources.

Key features

• QingKe 32-bit RISC-V4C core
• Support RV32IMAC instruction set and self-extending instructions
• Fast programmable interrupt controller + hardware interrupt stack
• Branch prediction, conflict handling mechanism
• Single-cycle multiplication, hardware division
• Multi-speed system main frequency, minimum 32KHz
• 512K-byte non-volatile memory FlashROM
• 448KB user application program memory area CodeFlash
• 32KB user non-volatile data memory area DataFlash
• 24KB system boot program memory area BootLoader
• 8KB system non-volatile configuration information memory area InfoFlash
• Support ICP, ISP and IAP, support OTA wireless upgrade
• Basically, zero-wait at the system frequency of 20MHz
• 26K-byte volatile data storage SRAM
• Sleep retention memory area RAM24K using 24KB dual power supply
• Sleep retention memory area RAM2K using 2KB dual power supply
• Support 3.3V and 2.5V power, CH592 supports 1.8V
• Built-in DC-DC conversion, reducing power consumption
• Idle mode: 1.1mA
• Halt mode: 1.0mA (PLL/HSE not stopped) 180uA (PLL/HSE stopped)
• Sleep mode: Multiple gears from 0.8uA to 2.5uA
• Shutdown mode: Multiple gears from 0.3uA to 1.3uA
• Bluetooth receive current when DC-DC is off at 3.3V: 7.5mA
• 3.3V enable DC-DC, Bluetooth receive current: 3.5mA
• Optional low-voltage monitoring of low-power or high-precision battery voltage
• AES-128 encryption and decryption, unique chip ID
• Integrated with 2.4GHz RF transceiver and baseband and link control
• -95dBm RX sensitivity, programmable +4.5dBm TX power
• BLE complies with Bluetooth Low Energy Specification 5.4
• Support 2Mbps, 1Mbps
• Provide optimized protocol stack and application layer API, and support networking
• 2 modes of timing and triggering
• Supports 80-dot (20*4) LCD panel
• Integrated USB 2.0 full-speed transceiver PHY, no peripheral required
• 15 endpoints, support DMA, support 64-byte data packet
• Support host and device mode at full-speed/lowspeed
• 12-bit analog to digital converter, support differential and single-ended input
• 12 external analog signal channels and 2 internal signal channels
• 12-channel
• 4 sets of 26-bit timers, which can reach 4.2S at the frequency of 16MHz
• 4-channel capture/sample, support rising edge/falling edge /double edge
• 4-channel 26-bit PWM output
• 8-channel 8-bit PWM output, the first 6 channels support 16-bit PWM output
• 4 independent UARTs, compatible with 16C550, built-in 8-level FIFO
• 23-bit counter, up to 6Mbps communication baud rate
• UARTO supports some Modem, supports hardware automatic flow control
• UARTO supports automatic matching of slave address during multi-device communication
• Support Master and Slave modes
• Built-in FIFO, Support DMA
• SCK serial clock frequency can reach half of system clock frequency
• Support Master and Slave modes, compatible with SMBus
• Support 7-bit or 10-bit address and bus broadcast
• Support arbitration, error detection, PEC check and clock extension
• Built-in PLL, built-in 32KHz clock
• 24 GPIOs, 4 of them support 5V signal input
• Optional pull-up or pull-down resistor, optional output drive capability
• 24 GPIOs support level or edge interrupt input
• 24 GPIOs support level or edge wake-up input
• Package: QFN, TSSOP