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TJA1043T/1J4.5V~5.5V CAN FD Transceiver 5Mbps SOIC-14 Drivers, Receivers, Transceivers RoHS
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₹94.90
3,16,545 in stock

3V~3.6V Transmitter 5.7Gbps TQFP-100(14x14) Drivers, Receivers, Transceivers RoHS
Dual Pixel LVDS Display Interface / FPD-Link
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement · policy
168 in stock
#C192856
Stock & price checked 4 days ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 1+ | ₹1,015.68 | ₹1,015.68 |
| 10+ | ₹872.68 | ₹8,726.80 |
| 30+ | ₹785.47 | ₹23,564.10 |
| 90+ | ₹712.44 | ₹64,119.60 |
1 × ₹1,015.68
₹1,015.68
excl. GST
₹1,198.50 incl. 18% GST
DS90C387AVJD/NOPB
₹1,015.68 for 1 + GST
The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24- bit color) of CMOS/TTL data and 8 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second). The LDI chipset is improved over prior generations of FPDLink devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre- emphasis feature that provides additional output current during transitions to counteract cable loading effects. The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPDLink Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24- bit or 18- bit FPD- link receivers. This chipset is an ideal means to solve EMI and cable size problems for high- resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high- resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements.
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