DSPIC33CK64MC103-I/M5

Key features

• 16-Bit Wide Data Path
• Code Efficient (C and Assembly) Architecture
• 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle, Mixed-Sign Multiply: 32-bit multiply support
• Fast Six-Cycle Divide
• Zero Overhead Looping
• Four PWM Pairs
• Up to 2 ns PWM Resolution
• Dead Time for Rising and Falling Edges
• Dead-Time Compensation
• Clock Chopping for High-Frequency Operation
• PWM Support for: DC/DC, AC/DC, inverters, PFC, lighting; BLDC, PMSM, ACIM, SRM motors
• Fault and Current Limit Inputs
• Flexible Trigger Configuration for ADC Triggering
• Up to 15 A/D inputs
• 12-Bit Resolution
• One Shared SAR ADC Core
• Up to 3.5 Msps Conversion Rate per Core
• Dedicated Result Buffer for Each Analog Channel
• Flexible and Independent ADC Trigger Sources
• Four Digital Comparators
• Four Oversampling Filters
• Small Pin Count Packages Ranging from 28 to 48 Pins, Including UQFN as Small as 4x4 mm
• High-Current I/O Sink/Source
• Edge or Level Change Notification Interrupt on I/O Pins
• Peripheral Pin Select (PPS) Remappable Pins
• Up to 64 Kbytes Flash Memory: 10,000 erase/write cycle endurance; 20 years minimum data retention; Self-programmable under software control; Programmable code protection; Error Code Correction (ECC); Flash OTP by ICSP Write Inhibit
• Eight Kbytes SRAM Memory: SRAM Memory Built-In Self-Test (MBIST)
• Multiple Interrupt Vectors with Individually Programmable Priority
• Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Reserved Interrupt Handling
• Four External Interrupt Pins
• Watchdog Timer (WDT)
• Windowed Deadman Timer (DMT)
• Fail-Safe Clock Monitor (FSCM) with Dedicated Oscillator
• Selectable Oscillator Options Including: High-precision, 8 MHz internal Fast RC (FRC) Oscillator; Primary high-speed, crystal/resonator oscillator or external clock; Primary PLL, which can be clocked from FRC or crystal oscillator
• Low-Power Management modes (Sleep and Idle)
• Power-on Reset and Brown-out Reset
• On-Board Capacitorless Regulator
• 384 Bytes of One-Time-Programmable (OTP) Memory
• Two Four-Wire SPI modules (up to 50 Mbps): 16-byte FIFO; Variable width; I²S mode
• One I²C Host and Client w/Address Masking and IPMI Support
• Three Protocol UARTs with Automated Handling Support for: LIN 2.2; DMX; Smart card (ISO 7816)
• One SENT module
• Timers/Counters: One dedicated 16-bit timer/counter
• Four Single Output Capture/Compare/PWM/Timer (SCCP) modules: Flexible configuration as PWM, input capture, output compare or timers; Two 16-bit timers or one 32-bit timer in each module; PWM resolution down to 2.5 ns; Single PWM output
• One Quadrature Encoder Interface (QEI): Four inputs: Phase A, Phase B, Home, Index; One 32-bit timer/counter (in QEI module, available if encoder is not used)
• Reference Clock Output (REFCLKO)
• Four Configurable Logic Cells (CLC) with Internal Connections to Select Peripherals and PPS
• Four-Channel Hardware DMA
• 32-Bit CRC Calculation module
• Peripheral Trigger Generator (PTG): 16 possible trigger sources to other peripheral modules; CPU-independent state machine-based instruction sequencer; Two 16-bit general purpose timers
• One Fast Analog Comparator with Input Multiplexing
• Three Operational Amplifiers
• One 12-Bit PDM DAC with Slope Compensation
• One Output DAC Buffer
• Three Programming and Debugging Interfaces: Two-wire ICSP interface with non-intrusive access and real-time data exchange with application
• Three Complex, Five Simple Breakpoints
• IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan
• AEC-Q100 REV G (Grade 1: -40°C to +125°C)
• AEC-Q100 REV G (Grade 0: -40°C to +150°C)
• Backup Fast RC Oscillator (BFRC)
• Brown-out Reset (BOR)
• Capless Internal Voltage Regulator
• Clock Monitor System with Backup Oscillator
• CodeGuard Security
• Cyclic Redundancy Check (CRC)
• Dual Watchdog Timer (WDT)
• Fail-Safe Clock Monitoring (FSCM)
• Flash Error Correcting Code (ECC)
• Flash OTP by ICSP Write Inhibit
• RAM Memory Built-In Self-Test (MBIST)
• Two-Speed Start-up
• Virtual Pins for Redundancy and Monitoring
• Windowed Deadman Timer (DMT)
• Class B Safety Library – IEC 60730
• For ASIL B and Beyond Applications – ISO 26262
• FMEDA Computation Spreadsheet (evaluation of Random Hardware Failures Metric)
• Functional Safety Manual
• Functional Safety Diagnostics Suite