F280033SPZ

Others 32 Bit 120MHz LQFP-100(14x14) Microcontrollers RoHS

LQFP-100(14x14)ROHS3 CompliantActive

Manufacturer: TI
Manufacturer part #: F280033SPZ
Store part #: C20345408
Package / case: LQFP-100(14x14)
Category: Microcontrollers
Packaging: Bag-packed

Datasheet (PDF)

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17 in stock

#C20345408

Stock & price checked 10 days ago

Quantity	Unit price	Pack price
1+	₹1,213.65	₹1,213.65
10+	₹1,034.20	₹10,342.00
30+	₹924.71	₹27,741.30
90+	₹832.93	₹74,963.70

Quantity (min 1)

1 × ₹1,213.65

₹1,213.65

excl. GST

₹1,432.11 incl. 18% GST

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Standard pack: 90 per bag

F280033SPZ

₹1,213.65 for 1 + GST

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Specifications

DAC (Bit): 12bit
ADC (Bit): 12bit
Number of I/O: 55
Operating Temperature: -40℃~+125℃
Voltage - Supply: 3.3V
Program Memory Type: FLASH
Program Storage Size: 384KB
CPU Core: Others
Core Size: 32 Bit
CPU Maximum Speed: 120MHz
Oscillator Type: Built-in+External

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: 5A992C
Packaging: Bag-packed
Standard pack: 90 / Bag
Sold per: Piece
Minimum order: 1
Unit weight: 0.7 g

Overview

Applications

Home appliances
Air conditioner outdoor units
Building automation
Door drive control
Industrial machinery and machine tools
Automatic sorting equipment
Textile machinery
AC inverters and variable frequency drives
AC drive control modules
AC drive position feedback
AC drive power stage modules
Linear motor transport systems
Linear motor power stages
Single-axis and multi-axis servo drives

Key features

TMS320C28x 32-bit DSP core, operating at 120 MHz
IEEE 754 FPU support
Fast integer division (FINTDIV) support
Trigonometric Math Unit (TMU) support
Nonlinear PID (NLPID) control support
CRC engine and instructions (VCRC) support
Ten hardware breakpoints (with ERAD)
Programmable Control Law Accelerator (CLA)
Operating frequency 120 MHz
IEEE 754 single-precision floating-point instructions support
Executes code independently of the main CPU
On-chip memory
Three independent banks totaling 384KB (192KW) flash (ECC-protected)
69KB (34.5KW) RAM (ECC-protected)
Security features
JTAGLOCK
Zero-pin boot
Dual-zone security
Clock and system control
Two internal 10 MHz oscillators
Crystal oscillator or external clock input
Windowed watchdog timer module
Clock loss detection circuit
Dual Clock Comparator (DCC)
3.3-V I/O design
Internal VREG generation supports single-supply design
Brown-Out Reset (BOR) circuit
System peripherals
6-channel DMA controller
55 individually programmable multiplexed GPIO pins
23 digital inputs on analog pins
2 digital I/O (AGPIO) on analog pins
Enhanced Peripheral Interrupt Expansion (ePIE)
Multiple LPM support
Embedded Real-Time Analysis and Diagnostics (ERAD)
Unique ID (UID) number
Communication peripherals
One PMBus interface
Two I2C interfaces
One CAN/DCAN bus port
One CAN FD/MCAN bus port
Two SPI ports
Two UART-compatible SCI interfaces
Two UART-compatible LIN interfaces
FSI with one transmitter and one receiver (up to 200 Mbps)
Analog subsystem
Three 4-MSPS, 12-bit ADCs
Up to 23 external channels (including two GPDAC outputs)
Four integrated Post-Processing Blocks (PPB) per ADC
Four windowed comparators (CMPSS) with 12-bit reference DAC
Digital glitch filter
Two 12-bit buffered DAC outputs
Enhanced control peripherals
16 ePWM channels, eight with high-resolution capability (150 ps resolution)
Integrated dead-band support
Integrated hardware Trip Zones (TZs)
Three enhanced capture (eCAP) modules
One of the three eCAP modules supports High-Resolution Capture (HRCAP)
Two enhanced quadrature encoder pulse (eQEP) modules with CW/CCW operation mode support
Eight Sigma-Delta Filter Module (SDFM) input channels (two parallel filters per channel)
Standard SDFM data filtering
Comparator filter for fast response to over- or under-value conditions
Embedded Pattern Generator (EPG)
Configurable Logic Block (CLB)
Enhanced existing peripheral capabilities
Position manager solution support
Host Interface Controller (HIC)
External host access to internal memory
Background CRC (BGCRC)
Single-cycle CRC computation on 32-bit data
AES accelerator
Live Firmware Update (LFU)
Fast context switching from old to new firmware
Flash bank erase time improvement
Diagnostic features
Memory Power-On Self-Test (MPOST)
Hardware Built-In Self-Test (HWBIST)
Functional safety compliance (PZ and Q100 PM packages only)
Developed for functional safety applications
Documentation provided to assist ISO 26262 and IEC 61508 system design
System capability up to ASIL D and SIL 3
Hardware capability up to ASIL B and SIL 2
Safety-related certification
TÜV SÜD certified to ISO 26262, up to ASIL B and SIL 2 (PZ and Q100 PM packages only)
Package options
100-pin LQFP [PZ suffix]
80-pin LQFP [PN suffix]
64-pin LQFP [PM suffix]
48-pin LQFP [PT suffix]
Temperature options
Ambient temperature (TA): –40°C ~ 125°C
Junction temperature (TJ): –40°C ~ 150°C