FT61F020-URT

Key features

• 8-bit EEPROM-based RISC MCU
• Program: 2k x 14; RAM: 128 x 8; Data: 256 x 8
• 6 / 8 / 10 / 14 / 16 pins
• ADC: True 10-bit accuracy
• 7 timers, 4 independent PWM channels
• 1 enhanced capture/compare/PWM (with dead-band control)
• 2 analog comparators, 2 voltage regulator outputs
• Low standby, WDT and operating current
• POR, LVR, LVD
• High ESD, high EFT
• Low VDD operating voltage
• 37 RISC instructions: 2T or 4T
• 16 MHz / 2T (VDD ≥ 2.7)
• Up to 16 pins
• PROGRAM: 2k x 14 bit (read/write protection)
• DATA: 256 x 8 bit
• RAM: 128 x 8 bit, 8-level hardware stack
• 1M erase/write cycles (typical)
• >20 years / 85°C retention (typical)
• ESD > 4 kV, EFT > 5.5 kV
• True 10-bit accuracy (≤ 1 MHz ADC clock)
• 7 + 1 channel VADC-REF
• Internal: 2.0, 3.0, VDD
• External: VREF pin
• PWM modes: single PWM, half-bridge, full-bridge
• 3 PWM pairs (6 I/Os): complementary output + dead-band
• Single-pulse mode
• Identical period and duty cycle
• Selectable polarity
• SLEEP operation supported
• Independent: period, duty cycle, polarity
• Buzzer mode
• WDT (16-bit): 7-bit postscaler
• Timer0 (8-bit): 8-bit prescaler
• Timer1 (16-bit): 3-bit prescaler with gate control
• Timer2 (8-bit): 4-bit prescaler and postscaler
• Timer3/4/5 (12-bit): 7-bit prescaler and 8-bit postscaler
• SLEEP operation supported: 1 or 2x {instruction clock, HIRC}, LP, T0CK, T1CK
• Pull-up/pull-down resistors
• All I/O source current: 30mA (5V, 25°C)
• All I/O sink current: 23mA (5V, 25°C)
• 8 I/Os: interrupt/wake-up
• SLEEP
• LVR: 2.0, 2.2, 2.5, 2.8, 3.1, 3.6, 4.1 (V)
• LVD: 2.0, 2.4, 2.8, 3.0, 3.6, 4.0 (V)
• HIRC high-speed internal oscillator
• 16 MHz < ±1.5% typical (2.5−5.5V, 25°C)
• Divider: 1, 2, 4, 8, 16, 32, 64
• LIRC low-power low-speed internal oscillator
• 32 kHz or 256 kHz
• EC external clock (I/O input)
• LP / XT crystal input
• Dual-speed clock start-up (HIRC or LIRC)
• Fail-safe clock monitor
• On-chip debug (OCD), ISP
• 3 hardware breakpoints
• Software reset, halt, single-step, run, etc.