HC32F146KATA-LQFP64

The HC32F146 series are 32-bit MCUs based on the ARM Cortex-M0+ core, offering higher efficiency and lower power consumption compared to traditional CPU cores. The wide operating voltage range supports both 3V and 5V systems simultaneously. The devices integrate rich peripheral resources including UART, SPI, I²C, LCDC display module, 12-bit high-speed ADC, and operational amplifiers. This product is the first 5V device on the M0+ platform.

Applications

• Industrial instruments: field instruments, automotive and motorcycle dashboards
• Industrial control: inverters, UPS
• Body control: wipers, windows, central locking

Key features

• 32-bit ARM Cortex-M0+ core
• Processor revision: r0p1
• Maximum operating frequency: 48MHz
• NVIC: supports 1-channel NMI and 32-channel peripheral interrupts, 4 configurable interrupt priority levels
• 24-bit SysTick timer for OS task management
• Bit Band operation support
• On-chip Flash up to 128KB with code encryption protection, supports read wait states (0 or 1 cycle)
• On-chip SRAM up to 8KB
• DMA controller (2 channels): dedicated DMA bus for CPU, operates concurrently with CPU; 2 independently configurable channels; transfer triggered by software or built-in peripheral requests; transfer address space: 32-bit (4GB); transfer modes: block/burst/request; transfer data types: byte/half-word/word; transfer block count: 1–16; transfer count: 1–65536
• LCD controller (LCDC): supports internal resistor divider, external resistor divider, and external capacitor divider modes; selectable 40SEG × 4COM (max), 38SEG × 6COM (max), or 36SEG × 8COM (max); 4COM mode: selectable 1/2, 1/3, or 1/4 duty cycle, selectable 1/2 or 1/3 bias; 6COM mode: 1/6 duty cycle, selectable 1/3 or 1/4 bias; 8COM mode: 1/8 duty cycle, selectable 1/3 or 1/4 bias; adjustable frame display frequency
• UART: full-duplex double-buffered; optional parity; dedicated baud rate generator; multiple error detection (parity error, frame error, overflow error); hardware flow control via CTS/RTS; baud rate compensation support
• SPI: full-duplex double-buffered; dedicated baud rate generator; overflow error detection; chip select function; data length: 5 to 16 bits
• I²C: standard mode (up to 100 kbps) / fast mode (up to 400 kbps)
• 12-bit ADC: successive approximation type; sampling/conversion period ≥20 clock cycles; conversion rate up to 1 Mbps; selectable priority conversion mode or scan conversion mode; built-in FIFO for conversion results; monotonic 12-bit conversion with no missing codes; adjustable sample-and-hold time and conversion rate; supports 16 external input channels and 2 internal signal source inputs (OPA0/OPA1); window threshold comparison function
• Composite timer (up to 4 channels): selectable operating mode per channel — 16-bit PWM mode, 16-bit PPG mode, 16/32-bit reload timer mode, 16/32-bit PWC mode
• General-purpose I/O ports: pins not used for external bus or peripheral functions are available as I/O; any I/O pin supports port relocation for peripheral function assignment; fast GPIO with single-cycle access; configurable internal pull-up resistor per port; configurable open-drain output per port; direct port pin level readback; selected port relocation pins support high-current output of 12mA
• Dual timer: two programmable 32/16-bit down counters; selectable operating modes — free-running mode, periodic mode (= reload mode), one-shot mode
• External interrupt controller: up to 16 external interrupt input pins; 1 NMI input pin
• Watchdog timer (2 channels): generates interrupt or reset upon timeout; two watchdog types — hardware watchdog and software watchdog; hardware watchdog uses internal low-speed RC oscillator, operational in all low-power modes except stop mode
• Timebase counter: capable of waking the system from low-power mode; clock source can be any clock except PLL clock
• Clock/Reset: five clock sources available (2 external oscillators, 2 internal RC oscillators); external high-speed OSC: 4MHz–16MHz; external low-speed OSC: 32.768 kHz; internal high-speed RC oscillator: 4MHz; internal low-speed RC oscillator: 32 kHz; internal PLL: up to 48MHz; Reset: RSTB pin reset, power-on reset, software reset, watchdog timer reset, LVD reset, clock monitor reset
• Clock monitor: monitors external clock anomalies against internal RC oscillator-generated clock; reset triggered upon detection of external oscillation failure (clock stop); interrupt or reset triggered upon detection of abnormal external frequency
• LVD: two LVD units — LVD1 and LVD2 — for DVCC voltage monitoring; adjustable detection threshold; configurable interrupt or reset when voltage falls below threshold
• Operational amplifier: two independent op-amp units
• Low-power modes: Sleep mode, Timer mode, Stop mode
• Peripheral clock gating: reduces system power consumption by gating unused peripheral clocks
• Debug interface: Serial Wire Debug (SW-DP), Micro Trace Buffer (MTB)
• Unique ID: fixed 80-bit unique identifier per device
• Wide supply voltage range: DVCC 2.7V – 5.5V