HK32F030R8T6A

The HK32F030xxxxA is based on the ARM Cortex-M0 core, operating at up to 96 MHz, with up to 64 Kbyte of on-chip Flash and 10 Kbyte of SRAM. By configuring the Flash controller registers, interrupt vector remapping within the main Flash region can be achieved. The HK32F030xxxxA supports conventional Flash Level 0/1/2 read/write protection and Flash code encryption. To meet various security application requirements, the HK32F030xxxxA provides a CRC hardware computation unit to verify the correctness and integrity of data transmission or data storage. The HK32F030xxxxA integrates multiple communication interfaces: 3 UART channels (up to 12 Mbit/s): including 2 USART channels and 1 LPUART channel. USART supports synchronous and asynchronous full-duplex or half-duplex communication, multi-master communication, LIN protocol, SmartCard protocol, and IrDA SIR encoding/decoding; RX and TX pin positions can be swapped in software; data reception wake-up is supported in MCU Stop mode. Up to 2 high-speed (up to 18 Mbit/s) SPI/I2S channels. SPI/I2S supports full-duplex or half-duplex communication with 4–16-bit data width, master/slave mode, TI mode, NSS pulse mode, automatic CRC verification, and I2S protocol. Up to 2 high-speed (up to 1 MHz) I2C channels. I2C supports 1 MHz/400 kHz/100 kHz transfer modes, master/slave mode, multi-master mode, 7-bit/10-bit address modes, and SMBus protocol. Data reception wake-up is supported in MCU Stop mode. The HK32F030xxxxA integrates 1 × 16-bit advanced PWM timer (4 PWM outputs total, 3 of which feature dead-time complementary output), 5 × 16-bit and 1 × 32-bit general-purpose PWM timers, 1 basic timer, and 1 × 16-bit low-power timer. The HK32F030xxxxA integrates analog circuitry: 1 × 12-bit ADC (16 analog input channels, differential pair input supported; sampling rate up to 1 MSPS), 1 × POR/PDR circuit, and 1 internal reference voltage (sampled via the on-chip ADC). The HK32F030xxxxA integrates a hardware division and square-root unit (DVSQ), which enhances software processing capability and enables faster response to external events. All pins of the HK32F030xxxxA — except power, ground, NRST, and BOOT — can be used as GPIO, peripheral I/O, or external interrupt inputs, maximizing the number of available signal pins in pin-constrained applications. The HK32F030xxxxA operates over a temperature range of -40℃ to +105℃ with a supply voltage of 1.8 V to 3.6 V, meeting the requirements of the vast majority of application environments.

Applications

• Programmable controllers
• Printers
• Scanners
• Motor drive and speed control
• IoT terminals such as water meters, electricity meters, and gas meters
• Drone flight controllers and gimbal control
• Toy products
• Home appliances
• Intelligent robots
• Smartwatches and fitness bands
• ETC

Key features

• CPU Core:
• ARM Cortex-M0
• Maximum clock frequency: 96 MHz
• 24-bit System Tick timer
• Interrupt vector remapping support (configured via Flash controller registers)
• Operating voltage range: Single power domain (main supply VDD): 1.8 V - 3.6 V
• Typical operating current:
• Run mode: 6.1 mA@96 MHz; 1.6 mA@8 MHz
• Sleep mode: 4.7 mA@96 MHz
• Stop mode:
• LDO full speed: 0.7 mA@3.3 V
• LDO low power: 60 μA@3.3 V
• Standby mode: 1.6 μA@3.3 V
• Shutdown mode: 0.4 μA@3.3 V
• Memory:
• Up to 64 Kbyte Flash
• Zero-wait-state bus cycle Flash access when CPU frequency ≤ 24 MHz
• Flash data security protection with independently configurable read and write protection
• Encrypted Flash instruction and data storage against physical attacks
• 10 Kbyte SRAM
• Data security: CRC hardware unit
• Clocks:
• External high-speed clock (HSE): 4–32 MHz, typical 8 MHz
• External low-speed clock (LSE): 32.768 kHz
• Internal high-speed clock (HSI): configurable at 8 MHz / 14 MHz / 56 MHz
• Internal low-speed clock (LSI): 40 kHz
• PLL clock: maximum output frequency 96 MHz
• Clock input from device pin
• Reset:
• External pin reset
• Power-on reset (POR/PDR)
• Software reset
• Watchdog (IWDG and WWDG) reset
• Low-power management reset
• Option byte loader reset
• Programmable Voltage Detector (PVD):
• 8-level adjustable detection voltage threshold
• Configurable rising-edge and falling-edge detection
• GPIO ports:
• Up to 55 GPIO pins
• Each GPIO pin configurable as external interrupt input
• Communication interfaces:
• 2× USART: master synchronous SPI and hardware flow control for modem, ISO 7816 interface, LIN, IrDA, auto baud rate detection, and wake-up from Stop mode
• Up to 2× high-speed SPI: 4- to 16-bit programmable data frame, with multiplexed I2S interface
• Up to 2× I2C: ultra-fast mode (1 MHz), SMBus and PMBus support; data reception wake-up from Stop mode
• 1× LPUART: asynchronous serial communication at minimum power, single-wire half-duplex, modem hardware flow control (CTS/RTS), and multiprocessor communication
• Timers and PWM generators:
• 1× 16-bit advanced timer (4 PWM outputs, 3 with dead-time complementary output and brake function)
• 5× 16-bit and 1× 32-bit general-purpose timers (TIM2/TIM3/TIM14/TIM15/TIM16/TIM17)
• 1× 16-bit basic timer (TIM6)
• On-chip analog:
• 1× 12-bit SAR ADC (up to 16 analog input channels)
• Maximum conversion rate: 1 MSPS
• Automatic continuous conversion and scan conversion
• DMA controller (7 channels): supports triggers from timers, ADC, SPI, I2C, USART, and other peripherals
• SWD debug interface
• ARM CoreSight debug components (ROM Table, DWT, and BPU)
• Custom DBGMCU debug controller (low-power mode emulation control, debug peripheral clock control, debug and trace interface assignment)
• Fixed-point division/square root unit:
• 32-bit fixed-point division with simultaneous quotient and remainder output
• High-precision 32-bit fixed-point square root
• RTC with alarm function for periodic wake-up from Stop or Standby mode
• Reliability: qualified to HBM 6000 V / CDM 2000 V / MM 200 V / LU 200 mA