N32L406RBL7

Key features

• Core: 32-bit ARM Cortex-M4 + FPU, single-cycle hardware multiply/divide, DSP instructions and MPU support; 2 KB instruction cache with flash accelerator for zero-wait program execution; up to 64 MHz, 80 DMIPS performance.
• Secure Memory: Up to 128 KB on-chip flash with encrypted storage, multi-user partition management, data protection, hardware ECC; 100K erase/write cycles, 10-year data retention; 256 KB data flash (select models); 24 KB SRAM — 16 KB SRAM1 (configurable retention in STOP2 mode) and 8 KB SRAM2 (configurable retention in Standby and STOP2 modes) with hardware parity.
• Low-Power Management: Standby mode 1.5 µA — all backup registers retained, I/O retained, optional RTC running, 8 KB SRAM2 retained, fast wakeup; STOP2 mode 3 µA — RTC running, 8 KB SRAM2 retained, CPU registers retained, I/O retained, fast wakeup; Run mode 60 µA/MHz @ 64 MHz; Low-power run mode: PLL off, MSIS as system clock, main regulator off, low-power regulator on, USB/CAN/crypto accelerator power off, other peripherals optional.
• Segment LCD driver, up to 176 segments (4×44) or 320 segments (8×40).
• High-Performance Analog: 1× 12-bit 4.5 Msps ADC, multi-resolution configurable, up to 8 Msps in 6-bit mode, up to 16 external single-ended input channels with differential mode support; 2× rail-to-rail op-amps with built-in up to 32× PGA; 2× high-speed analog comparators with 64-level adjustable reference, COMP1 operational in STOP2 mode; 1× 12-bit DAC at 1 Msps; internal 2.048 V independent voltage reference; integrated brown-out detection unit.
• Clocks: HSE: 4 MHz~32 MHz external crystal; LSE: 32.768 kHz external crystal; HSI: internal 16 MHz RC oscillator; MSIS: internal 100 kHz~4 MHz RC oscillator; LSI: internal 40 kHz RC oscillator; on-chip PLL; MCO: 1 configurable clock output (low-speed or high-speed).
• Reset: Power-on/brown-out/external pin reset; watchdog reset.
• Up to 64 GPIO pins.
• Communication Interfaces: 5× USART — 3× USART (ISO7816, IrDA, LIN support), 2× UART; 1× LPUART with STOP2 wakeup support; 2× SPI up to 16 Mbps with I2S support; 2× I2C up to 1 MHz, master/slave configurable, dual-address response in slave mode; 1× USB 2.0 full-speed device; 1× CAN 2.0A/B.
• 1× DMA controller, 8 channels, fully configurable source and destination addresses.
• 1× RTC with leap-year perpetual calendar, alarm events, periodic wakeup, internal/external clock calibration.
• Timers: 2× 16-bit advanced timers — input capture, complementary output, quadrature encoder input, up to 9.25 ns control resolution, 4 independent channels each with 3 channels supporting 6 complementary PWM outputs; 5× 16-bit general-purpose timers with 4 independent channels each — input capture/output compare/PWM; 2× 16-bit basic timers; 1× 16-bit low-power timer with dual-pulse counting, operational in STOP2 mode; 1× 24-bit SysTick timer; 1× 7-bit WWDG; 1× 12-bit IWDG.
• Programming: SWD/JTAG debug interface; UART and USB bootloader support.
• Security: On-chip crypto hardware accelerator; AES, DES, 3DES, SHA-1/224/256, SM1, SM3, SM4, and SM7 algorithm support; flash encryption, multi-user partition management unit.
• TRNG; CRC-16/32; write protection, multi-level read protection (L0/L1/L2); secure boot, encrypted firmware download, secure update; external clock failure detection, tamper detection; 96-bit UID and 128-bit user chip ID.
• Operating Conditions: Supply voltage: 1.8V~3.6V; operating temperature: -40℃~105℃; ESD: ±4 kV (HBM), ±1 kV (CDM).
• Packages: QFN32 (4mm×4mm), QFN32 (5mm×5mm), QFN48 (6mm×6mm), LQFP48 (7mm×7mm), QFN64 (8mm×8mm), LQFP64 (7mm×7mm), LQFP64 (10mm×10mm), LQFP80 (12mm×12mm).