NE555DR-DW

NE555DR is a precision timing circuit capable of generating accurate time delays or oscillations. It operates in astable or monostable mode with external resistor-capacitor timing control. The threshold and trigger levels are two-thirds and one-third of VCC, respectively, and can be adjusted via the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. When the trigger input is above the trigger level and the threshold input exceeds the threshold level, the flip-flop is reset and the output goes low. The reset input overrides all other inputs and can be used to initiate a new timing cycle. When the reset input goes low, the flip-flop is reset and the output goes low. When the output is low, a low-impedance path is provided between the discharge terminal and ground. The device supports output currents up to 200mA, operates over a supply voltage range of 5V to 15V, and the output levels are compatible with TTL inputs.

Applications

• Monostable
• Astable operation

Key features

• Astable or monostable mode
• Adjustable duty cycle
• Output current up to ±200mA
• Low quiescent current, 3mA typical