PCA9515ADP,118

The PCA9515A is a CMOS integrated circuit designed for I2C bus and SMBus systems. It retains all the operating modes and features of the I2C bus system. Meanwhile, it extends the I2C bus by buffering the data (SDA) and clock (SCL) lines, thus supporting two buses with a capacitance of 400 pF each. The capacitance limit of the I2C bus is 400 pF, which restricts the number of devices and the bus length. Using the PCA9515A allows system designers to isolate the two parts of the bus, so more devices can be accommodated or a longer bus length can be supported. It can also be used to operate two buses, one running at 5 V and the other at 3.3 V; or one at 400 kHz and the other at 100 kHz. When 400 kHz operation is required, the 100 kHz bus is isolated. Two or more PCA9515As cannot be used in series. The design of the PCA9515A does not allow this configuration. Since there is no direction pin, slightly different "legal" low voltage levels are used to avoid a locked state between the input and output. When a "regular low" signal is applied to the input of the PCA9515A, it will be propagated as a "buffered low" with a slightly higher value. When this "buffered low" is applied to another PCA9515A, PCA9516A, or PCA9518/A connected in series, the second PCA9515A, PCA9516A, or PCA9518/A will not recognize it as a "regular low" and will not propagate it as a "buffered low" again. The PCA9510/A, PCA9511/A, PCA9512/A, PCA9513/A, and PCA9514/A cannot be used in series with the PCA9515A, PCA9516A, or PCA9518/A, but they can be used in series with each other because they use shifting rather than static offset to avoid the locked state. The output pull-down of each internal buffer is set to approximately 0.5 V, while the input threshold of each internal buffer is set about 0.07 V lower than when the output internal drive is low. This prevents the occurrence of a locked state.

Key features

• 2-channel, bidirectional buffer
• I2C bus and SMBus compatible
• Active-high repeater enable input
• Open-drain input/output
• No latch-up operation
• Supports arbitration and clock stretching across repeater
• Supports Standard-mode and Fast-mode I2C bus devices and multi-master
• Power-off high-impedance I2C bus pins
• Operating supply voltage range: 2.3 V to 3.6 V
• 5.5 V tolerant I2C bus and enable pins
• 0 Hz to 400 kHz clock frequency (maximum system operating frequency may be less than 400 kHz due to added repeater delay)
• ESD protection exceeding 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
• Latch-up testing compliant with JEDEC standard JESD78, exceeding 100 mA
• Available packages: SO8, TSSOP8 (MSOP8), HWSON8