PIC12F1501-E/P

Key features

• C Compiler Optimized Architecture
• Only 49 Instructions
• Operating Speed: DC – 20 MHz clock input, DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context Saving
• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes: Two full 16-bit File Select Registers (FSRs), FSRs can read program and data memory
• 16 MHz Internal Oscillator Block: Factory calibrated to ±1%, typical, Software selectable frequency range from 16 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• Three External Clock modes up to 20 MHz
• Operating Voltage Range: 1.8V to 3.6V (PIC12LF1501), 2.3V to 5.5V (PIC12F1501)
• Self-Programmable under Software Control
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Programmable Low-Power Brown-out Reset (LPBOR)
• Extended Watchdog Timer (WDT): Programmable period from 1 ms to 256s
• Programmable Code Protection
• In-Circuit Serial Programming (ICSP) via Two Pins
• Enhanced Low-Voltage Programming (LVP)
• In-Circuit Debug (ICD) via Two Pins
• Power-Saving Sleep mode: Low-Power Sleep mode, Low-Power BOR (LPBOR)
• Integrated Temperature Indicator
• 128 Bytes High-Endurance Flash: 100,000 write Flash endurance (minimum)
• 1 Kwords Linear Program Memory Addressing
• 64 bytes Linear Data Memory Addressing
• High-Endurance Flash Data Memory (HEF): 128 bytes if nonvolatile data storage, 100k erase/write cycles
• Sleep Current: 20 nA @1.8V, typical
• Watchdog Timer Current: 260 nA @1.8V, typical
• Operating Current: 30 μA @ 1.8V, typical
• Analog-to-Digital Converter (ADC): 10-bit resolution, Four external channels, Three internal channels: Fixed Voltage Reference, Digital-to-Analog Converter (DAC), Temperature Indicator channel, Auto acquisition capability, Conversion available during Sleep
• 5-Bit Digital-to-Analog Converter (DAC): Output available externally, Positive reference selection, Internal connections to comparators and ADC
• One Comparator: Rail-to-rail inputs, Power mode control, Software controllable hysteresis
• Voltage Reference: 1.024V Fixed Voltage Reference (FVR) with 1x, 2x and 4x Gain output levels
• Six I/O Pins (1 Input-only Pin): High current sink/source 25 mA/25 mA, Individually programmable weak pull-ups, Individually programmable Interrupt-on-Change (IOC) pins
• Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler
• Enhanced Timer1: 16-bit timer/counter with prescaler, External Gate Input mode
• Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler
• Four 10-bit PWM modules
• Two Configurable Logic Cell (CLC) modules: 16 selectable input source signals, Four inputs per module, Software control of combinational/sequential logic/state/clock functions, AND/OR/XOR/D Flop/D Latch/SR/JK, Inputs from external and internal sources, Output available to pins and peripherals, Operation while in Sleep
• Numerically Controlled Oscillator (NCO): 20-bit accumulator, 16-bit increment, True linear frequency control, High-speed clock input, Selectable Output modes, Fixed Duty Cycle (FDC) mode, Pulse Frequency (PF) mode
• Complementary Waveform Generator (CWG): Eight selectable signal sources, Selectable falling and rising edge dead-band control, Polarity control, Four auto-shutdown sources, Multiple input sources: PWM, CLC, NCO