PIC18F45K50T-I/MV

Key features

• USB V2.0 Compliant
• Crystal-less Full Speed (12 Mb/s) and Low-Speed Operation (1.5 Mb/s)
• Supports Control, Interrupt, Isochronous and Bulk Transfers
• Supports up to 32 Endpoints (16 Bidirectional)
• 1 Kbyte Dual Access RAM for USB
• On-Chip USB Transceiver
• zx and 4xPLL Clock Multipliers
• Two External Clock modes, Up to 48 MHz (12 MIPS)
• Internal 31 kHz Oscillator
• Internal Oscillator, 31 kHz to 16 MHz - Factory calibrated to ± 1% - Self-tune to ± 0.20% max. from USB or secondary oscillator
• Secondary Oscillator using Timer1 ⨂32 kHz
• Fail-Safe Clock Monitor: - Allows for safe shutdown if any clock stops
• Up to 33 I/O pins plus 3 Input-Only Pins: - High-current Sink/Source 25 mA/25 mA - Three programmable external interrupts - 11 programmable interrupts-on-change - Nine programmable weak pull-ups - Programmable slew rate
• SR Latch
• Enhanced Capture/Compare/PWM (ECCP) module: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart - Pulse steering control
• Capture/Compare/PWM (CCP) module
• Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all four modes) and I²C Master and Slave modes
• Two Analog Comparators with Input Multiplexing
• 10-Bit Analog-to-Digital (A/D) Converter module: - Up to 25 input channels - Auto-acquisition capability - Conversion available during Sleep
• Digital-to-Analog Converter (DAC) module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection
• High/Low-Voltage Detect module
• Charge Time Measurement Unit (CTMU): - Supports capacitive touch sensing for touch screens and capacitive switches
• Enhanced USART module: - Supports RS-485, RS-232 and LIN/J2602 - Auto-wake-up on Start bit - Auto-Baud Detect
• Sleep mode: 20 nA, typical
• Watchdog Timer: 300 nA, typical
• Timer1 Oscillator: 800 nA @ 32 kHz
• Peripheral Module Disable
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture for Re-Entrant Code
• Power Management Features: - Run: CPU on, peripherals on, SRAM on - Idle: CPU off, peripherals on, SRAM on - Sleep: CPU off, peripherals off, SRAM on
• Priority Levels for Interrupts
• Self-Programmable under Software Control
• 8×8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming via Two Pins
• In-Circuit Debug (ICD) with Three Breakpoints via Two Pins
• Optional dedicated ICD/ICSP Port (44-pin TQFP Package Only)
• Wide Operating Voltage Range: - F devices: 2.3V to 5.5V - LF devices: 1.8V to 3.6V
• Flash Program Memory of 10,000 Erase/Write Cycles Minimum and 20-year Data Retention