PIC18F4680-I/ML

Key features

• Run: CPU on, peripherals on
• Idle: CPU off, peripherals on
• Sleep: CPU off, peripherals off
• Idle mode currents down to 5.8 μA typical
• Sleep mode currents down to 0.1 μA typical
• Timer1 Oscillator: 1.1 μA, 32 kHz, 2V
• Watchdog Timer: 2.1 μA
• Two-Speed Oscillator Start-up
• Four Crystal modes, up to 40 MHz
• 4x Phase Lock Loop (PLL) – available for crystal and internal oscillators
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 40 MHz
• Internal oscillator block: 8 user selectable frequencies, from 31 kHz to 8 MHz; Provides a complete range of clock speeds, from 31 kHz to 32 MHz when used with PLL; User tunable to compensate for frequency drift
• Secondary oscillator using Timer1 ×32 kHz
• Fail-Safe Clock Monitor - Allows for safe shutdown if peripheral clock stops
• C compiler optimized architecture with optional extended instruction set
• 100,000 erase/write cycle Enhanced Flash program memory typical
• 1,000,000 erase/write cycle Data EEPROM memory typical
• Flash/Data EEPROM Retention: >40 years
• Self-programmable under software control
• Priority levels for interrupts
• 8×8 Single Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT): Programmable period from 41 ms to 131s
• Single-Supply 5V In-Circuit Serial Programming (ICSP) via two pins
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V
• High current sink/source 25 mA/25 mA
• Three external interrupts
• One Capture/Compare/PWM (CCP1) module
• Enhanced Capture/Compare/PWM (ECCP1) module (40/44-pin devices only): One, two or four PWM outputs; Selectable polarity; Programmable dead time; Auto-Shutdown and Auto-Restart
• Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI (all 4 modes) and I²C Master and Slave modes
• Enhanced Addressable USART module: Supports RS-485, RS-232 and LIN 1.3; RS-232 operation using internal oscillator block (no external crystal required); Auto-Wake-up on Start bit; Auto-Baud Detect
• 10-bit, up to 11-channel Analog-to-Digital Converter module (A/D), up to 100 Ksps: Auto-acquisition capability; Conversion available during Sleep
• Dual analog comparators with input multiplexing
• Message bit rates up to 1 Mbps
• Conforms to CAN 2.0B ACTIVE Specification
• Fully backward compatible with PIC18XXX8 CAN modules
• Three modes of operation: Legacy, Enhanced Legacy, FIFO
• Three dedicated transmit buffers with prioritization
• Two dedicated receive buffers
• Six programmable receive/transmit buffers
• Three full 29-bit acceptance masks
• 16 full 29-bit acceptance filters w/ dynamic association
• DeviceNet data byte filter support
• Automatic remote frame handling
• Advanced error management features