PIC24FJ64GP202-I/ML

Key features

• Modified Harvard Architecture
• 64 Kbytes of Flash Memory
• 8 Kbytes of SRAM
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Fast RC (FRC) Internal Oscillator
• 96 MHz PLL option
• Multiple clock divide options
• Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory
• USB v2.0 On-The-Go (OTG) Dual Role Capable
• Can Act as either Host or Device
• Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB Operation in Host mode
• Full-Speed USB Operation in Device mode
• High-Precision PLL for USB
• USB Device mode Operation from FRC Oscillator
• No Crystal Oscillator Required
• Supports Up to 32 Endpoints (16 bidirectional)
• USB module can use any RAM location on the device as USB endpoint buffers
• On-Chip USB Transceiver with Interface for Off-Chip USB Transceiver
• Supports Control, Interrupt, Isochronous and Bulk Transfers
• On-Chip Pull-up and Pull-Down Resistors
• Up to 14-Channel, Software-Selectable 10/12-Bit Analog-to-Digital Converter
• 12-bit, 350K samples/second conversion rate (single Sample-and-Hold)
• 10-bit, 400K samples/second conversion rate (single Sample-and-Hold)
• Sleep mode operation
• Low-voltage boost for input
• Band gap reference input feature
• Core-independent windowed threshold compare feature
• Auto-scan feature
• Three Analog Comparators with Input Multiplexing
• Programmable reference voltage for comparators
• Sleep and Idle modes
• Selectively Shut Down Peripherals and/or Core for Substantial Power Reduction and Fast Wake-up
• Doze mode
• Allows CPU to Run at a Lower Clock Speed than Peripherals
• Alternate Clock modes
• Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
• Retention Sleep with On-Chip Ultra Low-Power Retention Regulator
• Fail-Safe Clock Monitor Operation
• Detects clock failure and switches to on-chip, low-power RC Oscillator
• Power-on Reset (POR), Brown-out Reset (BOR)
• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Programmable High/Low-Voltage Detect (HLVD)
• Flexible Watchdog Timer (WDT) with RC Oscillator for Reliable Operation
• Deadman Timer (DMT) for Safety-Critical Applications
• Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator
• Flash OTP by ICSP
• Write Inhibit
• CodeGuard Security
• ECC Flash Memory (64 Kbytes) with Fault Injection
• Single Error Correction (SEC)
• Double-Error Detection (DED)
• Customer OTP Memory
• Unique Device Identifier (UDID)
• Supply Voltage Range of 2.0V to 3.6V
• Operating Ambient Temperature Range of -40°C to +125°C
• On-Chip Voltage Regulators (1.8V) for Low-Power Operation
• ECC Flash Memory (64 Kbytes): 10,000 erase/write cycle endurance, typical
• Data retention: 20 years minimum
• Self-programmable under software control
• Flash OTP emulation
• 8-Kbyte SRAM
• Programmable Reference Clock Output
• In-Circuit Serial Programming (ICSP) and In-Circuit Emulation (ICE) via Two Pins
• JTAG Boundary Scan Support
• High-Current Sink/Source 18 mA/18 mA on all I/O Pins
• Independent, Low-Power 32 kHz Timer Oscillator
• Two-Channel DMA Controller
• Minimizes CPU overhead and increases data throughput
• Timer1: 16-Bit Timer/Counter with External Crystal Oscillator; Timer1 can Provide an A/D Trigger
• Timer2/3: 16-Bit Timer/Counter, can Create 32-Bit Timer; Timer3 can Provide an A/D Trigger
• Five MCCP modules, Each with a Dedicated 16/32-Bit Timer
• Five 2-output MCCP modules
• Two Variable Width, Serial Peripheral Interface (SPI) Ports on All Devices; Three Operation modes
• Three-wire SPI (supports all four SPI modes)
• Up to 32-byte deep FIFO buffer
• I2S mode
• Speed up to 25 MHz
• Two I²C Host and Client w/Address Masking, PMBus and IPMI Support
• Two UART modules
• LIN/J2602 bus support (auto-wake-up, Auto-Baud Detect, Break character support)
• RS-232 and RS-485 support
• rDA@ mode (hardware encoder/decoder functions)
• Five External Interrupt Pins
• Hardware Real-Time Clock and Calendar (RTCC)
• Peripheral Pin Select (PPS)
• Allows Independent I/O Mapping of Many Peripherals
• Configurable Interrupt-on-Change on All I/O Pins
• Each pin is independently configurable for rising edge or falling edge change detection
• Reference Clock Output with Programmable Divider
• Four Configurable Logic Cell (CLC) Blocks
• Two inputs and one output, all mappable to peripherals or I/O pins
• AND/OR/XOR logic and D/JK flip-flop functions