RP2354B

RP2350 is the new high- performance, secure microcontroller from Raspberry Pi. With a higher core clock speed, double the on- chip SRAM, more powerful Arm cores, optional RISC- V cores, new security features, and upgraded interfacing capabilities, RP2350 delivers a significant performance and feature boost over its predecessor, RP2040. RP2350 provides a comprehensive security architecture, built around Arm TrustZone for Cortex- M, and incorporating signed boot, 8KB of antifuse OTP for key storage, SHA- 256 acceleration, a hardware TRNG, and fast glitch detectors. These features, including the secure boot ROM, are extensively documented and available to all users without restriction: this transparent approach, which contrasts with the "security through obscurity" offered by legacy vendors, allows professional users to integrate RP2350 into products with confidence. The unique dual- core, dual- architecture capability of RP2350 allows users to choose between a pair of industry- standard Arm Cortex- M33 cores, and a pair of open- hardware Hazard3 RISC- V cores. Three high- performance Programmable I/O (PIO) co- processors, with a total of twelve independent state machines, support software- defined interfacing, with little or no CPU overhead. RP2350 offers best- in- class performance for a vast range of applications, from cost- optimised embedded computing, to secure applications requiring trusted firmware, to industrial IoT deployments with demanding I/O requirements. It is available in four package variants: with 30 or 48 GPIO pins, and with or without 2MB stacked flash memory.

Applications

• Cost-optimised embedded computing
• Secure applications requiring trusted firmware
• Industrial IoT deployments with demanding I/O requirements

Key features

• CPU:
• Dual Arm Cortex- M33 or dual Hazard3 RISC- V processors @150MHz
• Memory:
• 520 KB on-chip SRAM, in ten independent banks
• Support for up to 16 MB of external QSPI flash/PSRAM via dedicated QSPI bus; additional 16 MB flash/PSRAM accessible via optional second chip-select
• Peripherals:
• 2 x UART
• 2 x SPI controllers
• 2 x I2C controllers
• 24 x PWM channels
• 4/8 x ADC channels
• 1 x USB 1.1 controller and PHY, with host and device support
• 12 x PIO state machines
• Security features:
• Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP
• Protected OTP storage for optional boot decryption key
• Global bus filtering based on Arm or RISC- V security/privilege levels
• Peripherals, GPIOs, and DMA channels individually assignable to security domains
• Hardware mitigations for fault injection attacks
• Hardware SHA-256 accelerator