SN65LVDM1676DGGR

The SN65LVDM1676 and SN65LVDM1677 (integrated termination) are sixteen differential line transmitters or receivers (tranceivers) that use low-voltage differential signaling (LVDS) to achieve signaling rates up to 200 Mbps per transceiver configured as a receiver and up to 650 Mbps per transceiver configured as a transmitter. These products are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers are doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50-Ω load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of 100 mV with up to 1 V of ground potential difference between a transmitter and receiver. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of transceivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

Applications

• Point-to-point baseband data transmission over ~100Ω impedance media, including PCB traces, backplanes, or cables
• Synchronous parallel data transmission requiring precise timing alignment between clock and data

Key features

• Sixteen Low-Voltage Differential Transceivers. Designed for Signaling Rates up to 200 Mbps per Receiver or 650 Mbps per Transmitter.
• Simplex (Point-to-Point) or Half-Duplex (Multipoint) Interface
• Typical Differential Output Voltage of 340 mV Into a 50-Ω Load
• Integrated 10-Ω Line Termination on 'LVDM1677 Product
• Propagation Delay Time:
• Driver: 2.5 ns Typ
• Receiver: 3 ns Typ
• Driver is High Impedance When Disabled or With VCC < 1.5 V for Power Up/Down
• Glitch-Free Performance and Hot-Plugging Events
• Bus-Terminal ESD Protection Exceeds 12 kV
• Low-Voltage TTL (LVTTL) Logic Input Levels Are 5-V Tolerant
• Packaged in Thin Shrink Small-Outline Package With 20 mil Terminal Pitch