Varnitronics
SN65LVDS84AQDGGRQ1 TI
TI

SN65LVDS84AQDGGRQ1

Driver 3V~3.6V TFSOP-48-6.1mm Drivers, Receivers, Transceivers RoHS

TFSOP-48-6.1mmROHS3 CompliantActive

FlatLink TRANSMITTER

Manufacturer
TI
Manufacturer part #
SN65LVDS84AQDGGRQ1
Store part #
C3227598
Package / case
TFSOP-48-6.1mm
Packaging
Tape & Reel (TR)
Datasheet (PDF)

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100% Authentic · 30-Day Return or Replacement · policy

76 in stock

#C3227598

Stock & price checked 4 days ago

QuantityUnit pricePack price
1+₹662.55₹662.55
10+₹630.37₹6,303.70
30+₹610.93₹18,327.90
100+₹594.52₹59,452.00

1 × ₹662.55

₹662.55

excl. GST

₹781.81 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 15-18 working days
  • GST invoice with every order
  • Standard pack: 2,000 per reel

SN65LVDS84AQDGGRQ1

₹662.55 for 1 + GST

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Specifications

Type
Driver
Voltage - Supply
3V~3.6V
Operating Temperature
-40℃~+125℃
Number of Drivers
4
Features
Low power standby / automatic shutdown on failure
Level Standard
LVDS
Number of Receivers
0

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
EAR99
Packaging
Tape & Reel (TR)
Standard pack
2,000 / Reel
Sold per
Piece
Minimum order
1
Unit weight
0.35 g

Overview

The SN65LVDS84AQ FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A. When transmitting, data bits DO - D20 are each loaded into registers of the SN65LVDS84AQ upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The SN65LVDS84AQ requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low level. The SN65LVDS84AQ is characterized for operation over the full automotive temperature range of -40℃ to 125℃.

Applications

  • SVGA, XGA, SXGA data transfer from controller to display
  • Automotive applications

Key features

  • 21:3 Data Channel Compression at up to 196 Mbytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI
  • 21 Data Channels Plus Clock In Low-Voltage TTL Inputs and 3 Data Channels Plus Clock Out Low-Voltage Differential Signaling (LVDS) Outputs
  • Operates From a Single 3.3-V Supply and 89 mW (Typ)
  • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 0.54 mW When Disabled
  • Wide Phase-Lock Input Frequency Range: 31 MHz to 75 MHz
  • No External Components Required for PLL
  • Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • SSC Tracking Capability of 3% Center Spread at 50-kHz Modulation Frequency
  • Improved Replacement for SN75LVDS84 and NSC DS90CF363A 3-V Device
  • Qualified for Automotive Applications

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