STM8L051F3P6TR

Key features

• 5 low power modes: Wait, Low power run (5.1 μA), Low power wait (3 μA), Active-halt with RTC (1.3 μA), Halt (350 nA)
• Ultra-low leakage per I/O: 50 nA
• Fast wakeup from Halt: 5 μs
• Harvard architecture and 3-stage pipeline
• Max freq: 16 MHz, 16 CISC MIPS peak
• Up to 40 external interrupt sources
• Reset and supply management
• Low power, ultra-safe BOR reset with 5 selectable thresholds
• Ultra low power POR/PDR
• Programmable voltage detector (PVD)
• 32 kHz and 1 to 16 MHz crystal oscillators
• Internal 16 MHz factory-trimmed RC
• Internal 38 kHz low consumption RC
• Clock security system
• Low power RTC
• BCD calendar with alarm interrupt
• Digital calibration with +/-0.5 ppm accuracy
• LSE security system
• Auto-wakeup from Halt w/ periodic interrupt
• Memories
• 8 Kbytes of Flash program memory and 256 bytes of data EEPROM with ECC
• Flexible write and read protection modes
• 1 Kbyte of RAM
• TSSOP20
• DMA
• 4 channels supporting ADC, SPI, I²C, USART, timers
• 1 channel for memory-to-memory
• 12-bit ADC up to 1 Msps/28 channels
• Internal reference voltage
• Timers
• Two 16-bit timers with 2 channels (used as IC, OC, PWM), quadrature encoder
• One 8-bit timer with 7-bit prescaler
• 2 watchdogs: 1 Window, 1 Independent
• Beeper timer with 1, 2 or 4 kHz frequencies
• Communication interfaces
• Synchronous serial interface (SPI)
• Fast I²C 400 kHz
• SMBus and PMBus
• USART
• Up to 18 I/Os, all mappable on interrupt vectors
• Development support
• Fast on-chip programming and nonintrusive debugging with SWIM
• Bootloader using USART