STM8S005C6T6TR

Key features

• Max fcPu: 16 MHz Advanced STM8 core with Harvard architecture and 3-stage pipeline Extended instruction set
• Medium-density Flash/EEPROM
• Program memory: 32 Kbytes of Flash memory; data retention 20 years at 55 ℃ after 100 cycles
• Data memory: 128 bytes true data EEPROM; endurance up to 100 k write/erase cycles
• RAM: 2 Kbytes
• 2.95 V to 5.5 operating voltage
• Flexible clock control, 4 master clock sources
• Low-power crystal resonator oscillator
• External clock input
• Internal, user-trimmable 16 MHz RC
• Internal low-power 128 kHz RC
• Clock security system with clock monitor
• Power management
• Low-power modes (wait, active-halt, halt)
• Switch-off peripheral clocks individually
• Permanently active, low-consumption power-on and power-down reset
• Nested interrupt controller with 32 interrupts
• Up to 37 external interrupts on 6 vectors
• 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM)
• Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
• 8-bit basic timer with 8-bit prescaler
• Auto wakeup timer
• Window and independent watchdog timers
• UART with clock output for synchronous operation, SmartCard, IrDA, LIN
• SPI interface up to 8 Mbit/s
• I2C interface up to 400 Kbit/s
• 10-bit ADC, ±1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog
• Up to 38 I/Os on a 48-pin package including 16 high-sink outputs
• Highly robust I/O design, immune against current injection
• Embedded single-wire interface module (SWIM) for fast on-chip programming and nonintrusive debugging