TMS320F28069PZT

The F2806x Piccolo series microcontrollers (MCUs) power the C28x core and the CLA coupled with highly integrated control peripherals in devices with fewer pins. The code of the devices in this series is compatible with the legacy C28x-based code and features high analog integration. An internal voltage regulator enables single power rail operation. The high-resolution pulse width modulator (HRPWM) module has been enhanced to support dual-edge control (frequency modulation). An analog comparator with a 10-bit internal reference has been added to the device, which can directly control the ePWM output. The ADC can perform conversions within a fixed full-scale range of 0V to 3.3V and supports ratio-metric operation with VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency.

Applications

• Switching Mode Power Supply (SMPS)
• Solar Micro-Inverters and Converters
• Power Factor Correction (PFC)
• Smart Grid and Power Line Communication
• AC/DC Inverters

Key features

• High-efficiency 32-bit CPU (TMS320C28x)
• 90MHz (cycle time: 11.11ns)
• 16x16 and 32x32 multiply-and-accumulate (MAC) operations
• 16x16 dual MAC
• Harvard bus architecture
• Atomic operations
• Fast interrupt response and processing
• Unified memory programming model
• Efficient code (C/C++ and assembly)
• Floating-Point Unit (FPU)
• Native single-precision floating-point operations
• Programmable Control Law Accelerator (CLA)
• 32-bit floating-point math accelerator
• Code execution independent of main CPU
• Viterbi, Complex Math, and CRC Unit (VCU)
• Extended C28x instruction set supporting complex multiplication, Viterbi operations, and CRC
• Embedded Memory
• Up to 256KB Flash
• Up to 100KB RAM
• 2KB one-time programmable (OTP) ROM
• 6-channel DMA
• Low device and system cost
• 3.3V single supply
• No power sequencing required
• Integrated power-on reset and brown-out reset
• Low-power operating modes
• No analog support pins
• Endianness: Little-endian
• JTAG boundary scan support
• IEEE Standard 1149.1-1990 Test Access Port and Boundary Scan Architecture
• Clocking
• Two internal zero-pin oscillators
• On-chip crystal oscillator / external clock input
• Watchdog timer module
• Missing clock detection circuit
• PIE module supporting all peripheral interrupts
• Three 32-bit CPU timers
• Advanced control peripherals
• Up to 8 enhanced PWM (ePWM) modules
• 16 total PWM channels (supports 8 HRPWM)
• Independent 16-bit timer per module
• 3 enhanced capture (eCAP) modules
• Up to 4 high-resolution capture (HRCAP) modules
• Up to 2 enhanced quadrature encoder pulse (eQEP) modules
• 12-bit ADC with dual sample-and-hold (S/H)
• Up to 3.46 MSPS
• Up to 16 channels
• On-chip temperature sensor
• 128-bit security key and lock
• Secure memory block protection
• Firmware reverse-engineering prevention
• Serial port peripherals
• Two SCI [UART] modules
• Two SPI modules
• One I²C bus
• One McBSP bus
• One eCAN
• USB 2.0 (see Device Comparison Table for availability)
• Full-speed device mode
• Full-speed or low-speed host mode
• Up to 54 individually programmable, multiplexed GPIO pins with input filtering
• Advanced emulation features
• Analysis and breakpoint capability
• Real-time hardware debugging
• 2806x packages
• 80-pin PFP and 100-pin PZP PowerPAD thermal-enhanced HTQFP
• 80-pin PN and 100-pin PZ LQFP