25AA02E48T-I/SN

The 25AA02E48/25AA02E64 (25AA02EXX) is a 2 Kbit Serial Electrically Erasable Programmable Read-Only Memory (EEPROM). The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 25AA02EXX is available in the standard 8-lead SOIC and 6-lead SOT-23 packages. The 25AA02EXX is a 256-byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in software to match the SPI protocol. The 25AA02EXX contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25AA02EXX in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25AA02EXX followed by an 8-bit address. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. Data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses to the slave. The internal Address Pointer automatically increments to the next higher address after each byte of data is shifted out. When the highest address is reached (FFh), the address counter rolls over to address 00h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin.

Key features

• Preprogrammed Globally Unique, 48-bit or 64-bit Node Address
• Compatible with EUI-48 and EUI-64
• 10 MHz Maximum Clock Frequency
• Low-Power CMOS Technology:
• Maximum Write Current: 5 mA at 5.5V
• Read Current: 5 mA at 5.5V, 10 MHz
• Standby Current: 1 μA at 2.5V
• 256x8-bit Organization
• Write Page Mode (up to 16 bytes)
• Sequential Read
• Self-Timed Erase and Write Cycles (5 ms maximum)
• Block Write Protection:
• Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
• Power-on/off data protection circuitry
• Write enable latch
• Write-protect pin
• High Reliability:
• Endurance: 1,000,000 erase/write cycles
• Data retention: > 200 years
• ESD protection: > 4000V
• Temperature Ranges Supported:
• Industrial (I): -40℃ to +85℃
• Pb-Free and RoHS Compliant