25LC080AT-I/SN

The 25AA080A/B, 25LC080A/B (25XX080A/B) are 8 Kbit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (\(\overline{{\mathsf{H O L D}}}\)). While the device is paused, transitions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. The 25XX080A/B is available in standard packages including 8 - lead PDIP and SOIC, and advanced packaging including 8 - lead MSOP, and 8 - lead TSSOP. All packages are Pb - free and RoHS compliant. The 25XX080A/B are 1024 byte Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) Port of many of today’s popular microcontroller families, including Microchip’s \(\mathsf{P}|\mathsf{C}^{\oplus}\) microcontrollers. It may also interface with microcontrollers that do not have a built - in Synchronous Serial Port by using discrete I/O lines programmed properly with the software. The 25XX080A/B contains an 8 - bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX080A/B in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. The device is selected by pulling \(\overline{{\mathsf{C S}}}\) low. The 8 - bit read instruction is transmitted to the 25XX080A/B followed by the 16 - bit address, with the six MSBs of the address being don’t care bits. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (03FFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the \(\overline{{\mathsf{C S}}}\) pin.

Key features

• Max. clock 10 MHz
• Low - power CMOS technology
• 1024x8 - bit organization
• 16 byte page (‘A’ version devices)
• 32 byte page (‘B’ version devices)
• Write cycle time: 5 ms max.
• Self - timed ERASE and WRITE cycles
• Block write protection - Protect none, 1/4, 1/2 or all of array
• Built - in write protection - Power - on/off data protection circuitry - Write enable latch - Write - protect pin
• Sequential read
• High reliability - Endurance: 1,000,000 erase/write cycles - Data retention: >200 years - ESD protection: >4000 V
• Pb - free and RoHS compliant
• Temperature ranges supported; - Industrial (I): - 40℃ to + 85℃ - Automotive (E): - 40℃ to + 125℃