Varnitronics
74AHC273PW,118 Nexperia
Nexperia

74AHC273PW,118

2V~5.5V 8 1 11ns@5V,50pF TSSOP-20 Flip Flops RoHS

TSSOP-20ROHS3 CompliantActive

Octal D-type flip-flop with reset; positive-edge trigger

Manufacturer
Nexperia
Manufacturer part #
74AHC273PW,118
Store part #
C554347
Package / case
TSSOP-20
Category
Flip Flops
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

10,725 in stock

#C554347

Stock & price checked 6 days ago

QuantityUnit pricePack price
5+₹40.91₹204.55
50+₹32.11₹1,605.50
150+₹28.34₹4,251.00
500+₹23.63₹11,815.00
2,500+₹21.54₹53,850.00
5,000+₹20.28₹1,01,400.00

5 × ₹40.91

₹204.55

excl. GST

₹241.37 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 7–10 working days
  • GST invoice with every order
  • Standard pack: 2,500 per reel

74AHC273PW,118

₹204.55 for 5 + GST

Specifications

Voltage - Supply
2V~5.5V
Number of Bits per Element
8
Operating Temperature
-40℃~+125℃
Series
74AHC Series
Synchronous/Asynchronous
Asynchronous
Number of Elements
1
Current - Output High(IOH)
8mA
Current - Output Low(IOL)
8mA
Setup Time
3ns
Quiescent Current
4uA
Hold Time
1ns
Propagation Delay
11ns@5V,50pF
Trigger Type
Rising Edge

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
EAR99
Packaging
Tape & Reel (TR)
Standard pack
2,500 / Reel
Sold per
Piece
Minimum order
5 (multiples of 5)
Unit weight
0.22 g

Overview

The 74AHC273; 74AHCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.

Key features

  • Wide supply voltage range from 2.0 to 5.5 V
  • Overvoltage tolerant inputs to 5.5 V
  • High noise immunity
  • CMOS low power dissipation
  • Balanced propagation delays
  • All inputs have Schmitt-trigger actions
  • Ideal buffer for MOS microcontroller or memory
  • Common clock and master reset
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
  • Input levels: For 74AHC273: CMOS level For 74AHCT273: TTL level
  • ESD protection:
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃

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