TI
SN74LVC1G08DCKR1.65V~5.5V 3.6ns@3.3V 10uA SC-70-5 Gates and Inverters RoHS
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₹7.06
3,30,040 in stock
NexperiaDatasheet (PDF)
74AUP1G09GW,125
Schmitt trigger 800mV~3.6V 12.7ns@3.0V,30pF 900nA TSSOP-5-1.3mm Gates and Inverters RoHS
TSSOP-5-1.3mmROHS3 CompliantActive
Low-power 2-input AND gate with open-drain
- Manufacturer
- Nexperia
- Manufacturer part #
- 74AUP1G09GW,125
- Store part #
- C554948
- Package / case
- TSSOP-5-1.3mm
- Category
- Gates and Inverters
- Packaging
- Tape & Reel (TR)
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement · policy
1,855 in stock
#C554948
Stock & price checked 3 days ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 1+ | ₹63.09 | ₹63.09 |
| 10+ | ₹49.16 | ₹491.60 |
| 30+ | ₹43.29 | ₹1,298.70 |
| 100+ | ₹35.89 | ₹3,589.00 |
| 500+ | ₹32.64 | ₹16,320.00 |
| 1,000+ | ₹30.68 | ₹30,680.00 |
1 × ₹63.09
₹63.09
excl. GST
₹74.45 incl. 18% GST
- Dispatch in 15-18 working days
- GST invoice with every order
- Standard pack: 3,000 per reel
74AUP1G09GW,125
₹63.09 for 1 + GST
Specifications
- Input Type
- Schmitt trigger
- output type
- Open-drain
- Logic Family
- 74AUP
- Voltage - Supply
- 800mV~3.6V
- Propagation Delay
- 12.7ns@3.0V,30pF
- Output Logic Level - Low
- 500mV
- Features
- Local shutdown mode;Overvoltage-tolerant input
- Input Logic Level - Low
- 700mV;900mV
- Operating Temperature
- -40℃~+125℃
- Input Logic Level - High
- 1.6V;2V
- Quiescent Current(Iq)
- 900nA
- Number of Channels
- 2;2
- Current - Output Low(IOL)
- 4mA
Packaging & compliance
- RoHS
- ROHS3 Compliant
- Lifecycle
- Active
- Moisture sensitivity
- MSL 1 (unlimited)
- ECCN
- EAR99
- Packaging
- Tape & Reel (TR)
- Standard pack
- 3,000 / Reel
- Sold per
- Piece
- Minimum order
- 1
- Unit weight
- 0.038 g
Overview
The 74AUP1G09 is a single 2-input AND gate with open-drain output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The l(OFF) circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Applications
- Partial power-down applications
Key features
- Wide supply voltage range from 0.8 V to 3.6 V
- CMOS low power dissipation
- High noise immunity
- Overvoltage tolerant inputs to 3.6 V
- Low static power consumption; l(CC) = 0.9 μA (maximum)
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Low noise overshoot and undershoot < 10 % of V(CC)
- IOFF circuitry provides partial Power-down mode operation
- Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
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