74AUP1G373GW-Q100H
D Latch 0.8V~3.6V 1 2.5ns TSSOP-6-1.3mm Latches RoHS
Low-power D-type transparent latch; 3-state
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100% Authentic · 30-Day Return or Replacement · policy
2,780 in stock
#C545852
Stock & price checked 5 days ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 5+ | ₹44.57 | ₹222.85 |
| 50+ | ₹34.94 | ₹1,747.00 |
| 150+ | ₹30.81 | ₹4,621.50 |
| 500+ | ₹25.65 | ₹12,825.00 |
| 3,000+ | ₹23.36 | ₹70,080.00 |
| 6,000+ | ₹21.99 | ₹1,31,940.00 |
5 × ₹44.57
₹222.85
excl. GST
₹262.96 incl. 18% GST
- Dispatch in 7–10 working days
- GST invoice with every order
- Standard pack: 3,000 per reel
74AUP1G373GW-Q100H
₹222.85 for 5 + GST
Specifications
- Quiescent Current
- 0.9uA
- Series
- 74AUP
- Logic Type
- D Latch
- Voltage - Supply
- 0.8V~3.6V
- Current - Output Low(IOL)
- 4mA
- Operating Temperature
- -40℃~+125℃
- Output Type
- Tri-State
- Current - Output High(IOH)
- 4mA
- Setup Time
- -0.1ns;0.3ns
- Number of Gates
- 1
- Hold Time
- -0.1ns
- Propagation Delay
- 2.5ns
Packaging & compliance
- RoHS
- ROHS3 Compliant
- Lifecycle
- Active
- ECCN
- EAR99
- Packaging
- Tape & Reel (TR)
- Standard pack
- 3,000 / Reel
- Sold per
- Piece
- Minimum order
- 5 (multiples of 5)
- Unit weight
- 0.023 g
Overview
The 74AUP1G373-Q100 is a single D-type transparent latch; 3-state. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Key features
- Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃
- Wide supply voltage range from 0.8 V to 3.6 V
- High noise immunity
- CMOS low power dissipation
- Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V)
- Low static power consumption; ICC = 0.9 μA (maximum)
- Latch-up performance exceeds 100 mA per JESD 78 Class II
- Overvoltage tolerant inputs to 3.6 V
- Low noise overshoot and undershoot <10 % of VCC
- IOFF circuitry provides partial Power-down mode operation
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Alternatives
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