74HC138D

The 74HC138 and 74HCT138 decode three binary-weighted address inputs (A0, A1, and A2) into eight mutually exclusive outputs (Ȳ0 to Ȳ7). The device features three enable inputs (Ē1, Ē2, and E3). All outputs are HIGH unless Ē1 and Ē2 are LOW and E3 is HIGH. This multiple-enable function allows easy parallel expansion to a 1-of-32 (5-to-32 line) decoder using only four '138 ICs and one inverter. By using one of the active-LOW enable inputs as a data input and the remaining enable inputs as strobes, the '138 can be used as an 8-output demultiplexer. Inputs include clamping diodes, enabling the use of current-limiting resistors to interface the inputs to voltages exceeding VCC.

Key features

• Wide supply voltage range: 2.0V ~ 6.0V
• High noise immunity
• CMOS low power consumption
• Latch-up performance exceeds 250mA
• Demultiplexing capability
• Multiple input enables for easy expansion
• Memory chip select decoding
• Active-low mutually exclusive outputs
• Input levels: 74HC138 CMOS compatible; 74HCT138 TTL compatible
• ESD protection: HBM meets ANSI/ESDA/JEDEC JS-001 Class 2, exceeds 3500V; CDM meets ANSI/ESDA/JEDEC JS-002 Class C3, exceeds 2000V
• Multiple package options
• Operating temperature range: -40℃ ~ +85℃ and -40℃ ~ +125℃