74HC138PW

The 74HC138 and 74HCT138 decode three binary-weighted address inputs (A0, A1, and A2) into eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2, and E3). Each output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple-enable function allows easy parallel expansion to a 1-of-32 (5-to-32 line) decoder using only four '138 ICs and one inverter. By using one of the active-LOW enable inputs as a data input and the remaining enable inputs as strobe signals, the '138 can be used as an eight-output demultiplexer. Inputs include clamping diodes, enabling the inputs to be connected to voltages exceeding VCC using current-limiting resistors.

Key features

• Wide operating voltage range: 2.0 V to 6.0 V
• High noise immunity
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Demultiplexing capability
• Multiple input enables for easy expansion
• Ideal for memory chip select decoding
• Active-low mutually exclusive outputs
• Input levels:
• 74HC138: CMOS level
• 74HCT138: TTL level
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3500 V
• CDM: ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
• Multiple package options
• Operating temperature range: -40 °C to +85 °C and -40 °C to +125 °C