74HC174D,653

The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Key features

• Wide supply voltage range from 2.0 to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Input levels: For 74HC174: CMOS level For 74HCT174: TTL level
• Six edge-triggered D-type flip-flops
• Asynchronous master reset
• Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0V to 6.0 V)
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C