74HC573PW

The 74HC573 and 74HCT573 are 8-bit D-type transparent latches with 3-state outputs. The devices feature a latch enable (LE) and an output enable (OE) input. When LE is HIGH, data on the inputs enters the latches. In this condition, the latches are transparent and the latch outputs will change with their corresponding D inputs. When LE is LOW, the latches store the information that was present at the inputs during the setup time before the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes, which enables the use of current-limiting resistors to interface inputs to voltages exceeding VCC.

Key features

• Wide operating voltage range: 2.0 V ~ 6.0 V
• High noise immunity
• Low-power CMOS
• Latch-up performance exceeds 250 mA
• Input levels:
• 74HC573: CMOS levels
• 74HCT573: TTL levels
• Inputs and outputs on opposite sides of package for easy microprocessor interfacing
• Usable as input or output port for microprocessors and microcomputers
• 3-state non-inverting outputs for bus applications
• Common 3-state output enable input
• JEDEC standard compliant:
• JESD8C (2.7 V ~ 3.6 V)
• JESD7A (2.0 V ~ 6.0 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Operating temperature range: -40°C ~ +85°C and -40°C ~ +125°C