Varnitronics
74LVC16373ADGG,118 Nexperia
Nexperia

74LVC16373ADGG,118

D Latch 2.7V~3.6V 2 2.4ns TSSOP-48-6.2mm Latches RoHS

TSSOP-48-6.2mmROHS3 CompliantActive

16-bit D-type transparent latch with 5V-tolerant inputs/outputs and 3-state function

Manufacturer
Nexperia
Manufacturer part #
74LVC16373ADGG,118
Store part #
C282344
Package / case
TSSOP-48-6.2mm
Category
Latches
Packaging
Tape & Reel (TR)
Datasheet (PDF)

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100% Authentic · 30-Day Return or Replacement · policy

11,768 in stock

#C282344

Stock & price checked 23 h ago

QuantityUnit pricePack price
1+₹108.99₹108.99
10+₹87.45₹874.50
30+₹76.58₹2,297.40
100+₹65.91₹6,591.00
500+₹59.39₹29,695.00
1,000+₹56.12₹56,120.00

1 × ₹108.99

₹108.99

excl. GST

₹128.61 incl. 18% GST

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  • Standard pack: 2,000 per reel

74LVC16373ADGG,118

₹108.99 for 1 + GST

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Specifications

Quiescent Current
0.1uA
Series
74LVC
Logic Type
D Latch
Voltage - Supply
2.7V~3.6V
Operating Temperature
-40℃~+125℃
Output Type
Tri-State
Setup Time
1ns
Number of Gates
2
Hold Time
0.9ns
Propagation Delay
2.4ns

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
Moisture sensitivity
MSL 1 (unlimited)
ECCN
EAR99
Packaging
Tape & Reel (TR)
Standard pack
2,000 / Reel
Sold per
Piece
Minimum order
1
Unit weight
0.3 g

Overview

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs. The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.

Applications

  • Converter for mixed 3.3V and 5V environments

Key features

  • Overvoltage tolerant inputs to 5.5 V
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power dissipation
  • MULTIBYTE flow-through standard pinout architecture
  • Multiple low inductance supply pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • All data inputs have bus hold (74LVCH16373A only)
  • IOFF circuitry provides partial Power-down mode operation
  • Complies with JEDEC standards: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

Alternatives

Similar parts — check the datasheet before substituting.

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74LVT16373ADGG,118#C548994Nexperia · TSSOP-48-6.2mm₹121.58 · 0 in stockView

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