74LVC1G74DP-JSM

The 74LVC1G74 is a single positive-edge-triggered D-type flip-flop with separate data (D) input, clock (CP) input, set (SD) and reset (RD) inputs, and complementary Q and Q̄ outputs. Set and reset are asynchronous active-LOW inputs that operate independently of the clock input. Data present at the D input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. For predictable operation, the D input must be stable for one setup time prior to the LOW-to-HIGH clock transition.

Key features

• Wide supply voltage range: 1.65V ~ 5.5V
• 5V-tolerant outputs, compatible with 5V logic interface
• ±24mA output drive (Vcc = 3.0V)
• CMOS low power consumption
• Inputs withstand up to 5V
• Operating temperature range: -40℃ ~ +125℃
• Package options: TSSOP8/VSSOP8/SOP8/XSON8 (1×1.35×0.32)-0.35/XSON8 (1×1.95×0.5)-0.5