74LVC2G74DP,125-JSM

The 74LVC2G74 is a single positive-edge-triggered D-type flip-flop with individual data, clock, set, and reset inputs, plus complementary Q and Q̄ outputs. Set and reset are asynchronous active-LOW inputs that operate independently of the clock input. Data present at the input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. To ensure predictable operation, the data input must remain stable for one setup time prior to the LOW-to-HIGH clock transition.

Key features

• Wide supply voltage range: 1.65V ~ 5.5V
• 5V-tolerant outputs, compatible with 5V logic interface
• ±24mA output drive capability (VCC = 3.0V)
• CMOS low power consumption
• Latch-up performance exceeds 250mA
• Operating temperature range: -40°C ~ +125°C
• Package: TSSOP8/VSSOP8