ADAU1979WBCPZ-RL

The ADAU1979 integrates four high-performance ADCs with AC-coupled inputs delivering 4.5 V rms performance. These ADCs employ a multibit Σ-Δ architecture with a continuous-time front end for low EMI performance. It features an I²C/SPI control port through which a microcontroller can adjust volume and many other parameters. The ADAU1979 operates from a single 3.3 V supply. The required digital DVDD supply is generated internally. A low-power architecture reduces device power consumption. The on-chip PLL derives the master clock from an external clock input or a frame clock (sample rate clock). When using the frame clock, no separate high-frequency master clock is needed in the system. The ADAU1979 is available in a 40-lead LFCSP package.

Applications

• Automotive audio systems
• Active noise cancellation systems

Key features

• Quad 4.5 V rms (typical) differential inputs
• On-chip PLL for master clock generation
• Low EMI design
• ADC dynamic range: 109 dB (typical)
• THD+N: −95 dB (typical)
• Selectable digital high-pass filter
• 24-bit stereo ADC, 8 kHz to 192 kHz sample rates
• Digital volume control with automatic soft ramp
• I²C/SPI controllable for enhanced flexibility
• Software-controllable pop-free mute
• Software shutdown
• Right-justified, left-justified, I²S, and TDM modes
• Master and slave operating modes
• 40-lead LFCSP package
• Qualified for automotive applications