AiP74AUP1G74YA8.TR

The AiP74AUP1G74 is a low-power, low-voltage single positive-edge-triggered D flip-flop with individual data, clock, set, and reset inputs, plus complementary Q and Q̄ outputs. Set and reset are asynchronous active-low inputs that operate independently of the clock. Data present at the input is transferred to the Q output on the rising edge of the clock. The data input must remain stable for one setup time prior to the rising edge to ensure predictable operation. Schmitt-trigger inputs on all pins allow the circuit to tolerate slow input signal rise and fall times over the 0.8V to 3.6V range. The device ensures extremely low static and dynamic power consumption across the entire VCC supply voltage range of 0.8V to 3.6V. The IOFF circuit makes this device fully suitable for applications using partial power-down schemes; it disables the outputs to prevent damaging backflow current into the circuit during power-down.

Key features

• Supply voltage range: 0.8V ~ 3.6V
• Low quiescent current; ICC = 1uA (max)
• Input voltage up to 3.6V
• IOFF circuitry supports partial power-down operation
• Operating temperature range: -40℃ ~ +125℃
• Package: TSSOP8/VSSOP8