Wuxi I-core Elec

AIP74LVC2G74YA8.TR

1.65V~5.5V 1 4.1ns@5V,50pF VSSOP-8 Flip Flops

VSSOP-8RoHSActive

Single D-type flip-flop with set and reset; positive edge trigger

Manufacturer: Wuxi I-core Elec
Manufacturer part #: AIP74LVC2G74YA8.TR
Store part #: C4945078
Package / case: VSSOP-8
Category: Flip Flops
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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100% Authentic · 30-Day Return or Replacement · policy

2,600 in stock

#C4945078

Stock & price checked 5 days ago

Quantity	Unit price	Pack price
5+	₹42.65	₹213.25
50+	₹32.80	₹1,640.00
150+	₹28.58	₹4,287.00
500+	₹23.31	₹11,655.00
3,000+	₹20.97	₹62,910.00
6,000+	₹19.55	₹1,17,300.00

Quantity (min 5, multiples of 5)

5 × ₹42.65

₹213.25

excl. GST

₹251.64 incl. 18% GST

Need volume or a scheduled delivery? Request a quote

Dispatch in 7–10 working days
GST invoice with every order
Standard pack: 3,000 per reel

AIP74LVC2G74YA8.TR

₹213.25 for 5 + GST

Specifications

Voltage - Supply: 1.65V~5.5V
Output Type: Complementary
Operating Temperature: -40℃~+105℃
Series: 74LVC Series
Synchronous/Asynchronous: Asynchronous
Number of Elements: 1
Current - Output High(IOH): 32mA
Current - Output Low(IOL): 32mA
Setup Time: 1.1ns
Quiescent Current: 4uA
Hold Time: 1ns
Propagation Delay: 4.1ns@5V,50pF
Trigger Type: Rising Edge

Packaging & compliance

RoHS: RoHS
Lifecycle: Active
Packaging: Tape & Reel (TR)
Standard pack: 3,000 / Reel
Sold per: Piece
Minimum order: 5 (multiples of 5)
Unit weight: 0.053 g

Overview

The AiP74LVC2G74 is a single positive-edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q(overline) outputs. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.