
CD4027NS16ARDQ
3V~18V 1 2 SOP-16 Flip Flops
CMOS Dual J-K Flip-Flop
- Manufacturer
- GR
- Manufacturer part #
- CD4027NS16ARDQ
- Store part #
- C22465476
- Package / case
- SOP-16
- Category
- Flip Flops
- Packaging
- Tape & Reel (TR)
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement · policy
1,870 in stock
#C22465476
Stock & price checked 5 days ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 5+ | ₹24.65 | ₹123.25 |
| 50+ | ₹19.36 | ₹968.00 |
| 150+ | ₹17.09 | ₹2,563.50 |
| 500+ | ₹14.26 | ₹7,130.00 |
| 2,500+ | ₹13.01 | ₹32,525.00 |
| 4,000+ | ₹12.24 | ₹48,960.00 |
5 × ₹24.65
₹123.25
excl. GST
₹145.44 incl. 18% GST
- Dispatch in 7–10 working days
- GST invoice with every order
- Standard pack: 4,000 per reel
CD4027NS16ARDQ
₹123.25 for 5 + GST
Specifications
- Voltage - Supply
- 3V~18V
- Number of Bits per Element
- 1
- Output Type
- Complementary
- Operating Temperature
- -40℃~+85℃
- Synchronous/Asynchronous
- Asynchronous
- Number of Elements
- 2
- Current - Output High(IOH)
- 1.5mA
- Current - Output Low(IOL)
- 30mA
- Quiescent Current
- 1uA
- Trigger Type
- Rising Edge
Packaging & compliance
- RoHS
- RoHS
- Lifecycle
- Active
- Packaging
- Tape & Reel (TR)
- Standard pack
- 4,000 / Reel
- Sold per
- Piece
- Minimum order
- 5 (multiples of 5)
- Unit weight
- 0.316 g
Overview
CD4027 is a single monolithic chip integrated circuit containing two identical complementarysymmetry J-K master-slave flip-flops. Each flip-flop has provisions for individual J, K,Set,Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the CD4013B dual D type flip-flop. The CD4027 is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal selfsteering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input.
Key features
- Set - Reset capability
- Static flip-flop operation - retains state indefinitely with clock level either “High” or “Low”
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 18V
- Maximum input current of 1μA at 18V and 25℃
- 5V, 10V, and 15V parametric ratings
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