Varnitronics
CD4043BPWR TI
TI

CD4043BPWR

SR Latch 3V~18V 4 50ns TSSOP-16 Latches RoHS

TSSOP-16ROHS3 CompliantActive

CMOS Quad 3-State R/S Latches

Manufacturer
TI
Manufacturer part #
CD4043BPWR
Store part #
C2652970
Package / case
TSSOP-16
Category
Latches
Packaging
Tape & Reel (TR)
Datasheet (PDF)

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11,197 in stock

#C2652970

Stock & price checked 6 days ago

QuantityUnit pricePack price
1+₹104.79₹104.79
10+₹88.75₹887.50
30+₹77.24₹2,317.20
100+₹67.91₹6,791.00
500+₹64.88₹32,440.00
1,000+₹63.13₹63,130.00

1 × ₹104.79

₹104.79

excl. GST

₹123.65 incl. 18% GST

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  • Standard pack: 2,000 per reel

CD4043BPWR

₹104.79 for 1 + GST

Specifications

Quiescent Current
0.04uA
Series
4000B
Logic Type
SR Latch
Voltage - Supply
3V~18V
Current - Output Low(IOL)
6.8mA
Operating Temperature
-55℃~+125℃
Output Type
Tri-State
Number of Gates
4
Current - Output High(IOH)
6.8mA
Propagation Delay
50ns

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
EAR99
Packaging
Tape & Reel (TR)
Standard pack
2,000 / Reel
Sold per
Piece
Minimum order
1
Unit weight
0.183 g

Overview

CD4043B types are quad crosscoupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3- state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch.states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The ppen circuit feature allows common busing of the outputs.

Applications

  • Hold registers in multi-register systems
  • 4-bit independent storage with output enable
  • Strobed registers
  • General-purpose digital logic
  • CD4043B for positive-logic systems
  • CD4044B for negative-logic systems

Key features

  • 3-state outputs with common output ENABLE
  • Separate SET and RESET inputs for each latch
  • NOR and NAND configurations
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20V
  • Maximum input current of μA at 78V over full package temperature range; 100 nA at 18 V and 25℃
  • Noise margin (over full package temperature range): 1 V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
  • Meets all requirements of JEDEC Tentative Standard No. 1aB, "Standard Specifications for Description of B' Series CMOS Devices"
  • Holding register in multi-register system
  • Four bits of independent storage with output ENABLE
  • Strobed register
  • General digital logic
  • CD4643B for positive logic systems
  • CD4044B for negative logic systems

Alternatives

Similar parts — check the datasheet before substituting.

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