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SN74LVC1G08DCKR1.65V~5.5V 3.6ns@3.3V 10uA SC-70-5 Gates and Inverters RoHS
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TIDatasheet (PDF)
CD4072BPW
3V~18V 90ns@15V,50pF 1uA TSSOP-14 Gates and Inverters RoHS
TSSOP-14ROHS3 CompliantActive
- Manufacturer
- TI
- Manufacturer part #
- CD4072BPW
- Store part #
- C2877139
- Package / case
- TSSOP-14
- Category
- Gates and Inverters
- Packaging
- Tube-packed
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement · policy
1,178 in stock
#C2877139
Stock & price checked 32 h ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 1+ | ₹81.71 | ₹81.71 |
| 10+ | ₹69.10 | ₹691.00 |
| 30+ | ₹60.20 | ₹1,806.00 |
| 100+ | ₹52.80 | ₹5,280.00 |
| 500+ | ₹50.63 | ₹25,315.00 |
| 1,000+ | ₹49.11 | ₹49,110.00 |
1 × ₹81.71
₹81.71
excl. GST
₹96.42 incl. 18% GST
- Dispatch in 7–10 working days
- GST invoice with every order
- Standard pack: 90 per tube
CD4072BPW
₹81.71 for 1 + GST
Specifications
- Logic Family
- 4000B Series
- Voltage - Supply
- 3V~18V
- Output Logic Level - Low
- 50mV
- Propagation Delay
- 90ns@15V,50pF
- Input Logic Level - High
- 3.5V~11V
- Operating Temperature
- -55℃~+125℃
- Input Logic Level - Low
- 1.5V~4V
- Output Logic Level - High
- 4.95V;9.95V;14.95V
- Quiescent Current(Iq)
- 1uA
- Number of Channels
- 2;4
- Current - Output High(IOH)
- 3.4mA
- Current - Output Low(IOL)
- 3.4mA
Packaging & compliance
- RoHS
- ROHS3 Compliant
- Lifecycle
- Active
- Moisture sensitivity
- MSL 1 (unlimited)
- ECCN
- EAR99
- Packaging
- Tube-packed
- Standard pack
- 90 / Tube
- Sold per
- Piece
- Minimum order
- 1
- Unit weight
- 1.4 g
Overview
CD4071B,CD4072B,and CD4075B OR gates provide the system designer with direct implementation of the positive- logic OR function and supplement the existing family of CMOS gates.
Applications
- Implementation of positive logic OR functions in digital system design
Key features
- Medium- Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10V
- 100% tested for quiescent current at 20V
- Maximum input current of 1μA at 18V over full package - temperature range; 100 nA at 18V and 25℃
- Standardized, symmetrical output characteristics
- Noise margin (over full package temperature range): 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
- 5 - V, 10 - V, and 15 - V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No.13B, Standard Specifications for Description of δ'B' Series CMOS Devices
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