CD74ACT109M96

The ’ACT109 devices contain two independent J-K(overline) positive-edge-triggered flip-flops. A low level at the preset PRE(overline) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR(overline) are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.

Key features

• TTL-compatible inputs
• Operating speed comparable to bipolar F, AS, and S series with significantly reduced power consumption
• Balanced propagation delay
• Output drive current: ±24mA
• Fan-out to 15 F-series devices
• CMOS process and circuit design with SCR latch-up protection
• ESD protection exceeding 2kV
• Supply voltage range: -0.5V~6V
• Input clamp current range: ±20mA
• Continuous output current range: ±50mA
• Continuous current at VCC or GND pins: ±100mA
• Thermal resistance: 67°C/W (E package), 73°C/W (M package)
• Storage temperature range: -65°C~150°C
• All unused inputs must be tied to VCC or GND to ensure proper device operation