CS8416-CZZR

A monolithic CMOS device that receives and decodes one of eight stereo pairs of digital audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3 interface standards. It has a serial digital audio output port and comprehensive control ability through a selectable control port in Software Mode or through selectable pins in Hardware Mode. Channel status data are assembled in buffers, making read access easy. GPO pins may be assigned to route a variety of signals to output pins. A low-jitter clock recovery mechanism yields a very clean recovered clock from the incoming AES3 stream. Stand-alone operation allows systems with no microcontroller to operate it with dedicated output pins for channel status data. Available in 28-pin TSSOP, SOIC, and QFN packages in Commercial grade (-10°C to +70°C) and Automotive grade (-40°C to +85°C).

Applications

• A/V receivers
• CD-R
• DVD receivers
• multimedia speakers
• digital mixing consoles
• effects processors
• set-top boxes
• computer and automotive audio systems

Key features

• Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF-Compatible Receiver
• +3.3 V Analog Supply (VA)
• +3.3 V Digital Supply (VD)
• +3.3 V or +5.0 V Digital Interface Supply (VL)
• 8:2 S/PDIF Input MUX
• AES/SPDIF Input Pins Selectable in Hardware Mode
• Three General Purpose Outputs (GPO) Allow Signal Routing
• Selectable Signal Routing to GPO Pins
• S/PDIF-to-TX Inputs Selectable in Hardware Mode
• Flexible 3-wire Serial Digital Output Port
• 32 kHz to 192 kHz Sample Frequency Range
• Low-Jitter Clock Recovery
• Pin and Microcontroller Read Access to Channel Status and User Data
• SPI or I²C Control Port Software Mode and Stand-Alone Hardware Mode
• Differential Cable Receiver
• On-Chip Channel Status Data Buffer Memories
• Auto-Detection of Compressed Audio Input Streams
• Decodes CD Q Sub-Code
• OMCK System Clock Mode