EN25QH64A-104HIP

The EN25QH64A is a 64 Megabit (8,192K-byte) Serial Flash memory, with advanced write protection mechanisms. The EN25QH64A supports the single bit and four bits serial input and output commands via standard Serial Peripheral Interface (SPI) pins: Serial Clock, Chip Select, Serial DQ0 (DI) and DQ1(DO), DQ2(WP#) and DQ3 (HOLD#/RESET#). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 416MHz (104Mhz x 4) for Quad Output while using the Quad Output Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The EN25QH64A also offers a sophisticated method for protecting individual blocks against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect blocks, a system can unprotect a specific block to modify its contents while keeping the remaining blocks of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. The EN25QH64A is designed to allow either single Sector/Block at a time or full chip erase operation. The EN25QH64A can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector or block.

Key features

• Single power supply operation
• Full voltage range: 2.7 - 3.6 volt
• Serial Interface Architecture
• SPI Compatible: Mode 0 and Mode 3
• 64 M-bit Serial Flash
• 64 M-bit / 8,192 KByte /32,768 pages
• 256 bytes per programmable page
• Standard, Dual or Quad SPI
• Standard SPI: CLK, CS#, DI, DO, WP#, HOLD#/RESET#
• Dual SPI: CLK, CS#, DQ0, DQ1, WP#, HOLD#/RESET#
• Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
• Configurable dummy cycle number
• High performance
• Normal read - 83MHz
• Fast read - Standard SPI: 104MHz with 1 dummy bytes - Dual SPI: 104MHz with 1 dummy bytes - Quad SPI: 104MHz with 3 dummy bytes
• Low power consumption
• 5 mA typical active current
• 1μA typical power down current
• Uniform Sector Architecture:
• 2048 sectors of 4-Kbyte
• 256 blocks of 32-Kbyte
• 128 blocks of 64-Kbyte
• Any sector or block can be erased individually
• Software and Hardware Write Protection:
• Write Protect all or portion of memory via software
• Enable/Disable protection with WP# pin
• Software and Hardware Reset
• High performance program/erase speed
• Page program time: 0.5ms typical
• Sector erase time: 40ms typical
• Half Block erase time 200ms typical
• Block erase time 300ms typical
• Chip erase time: 30 Seconds typical
• Volatile Status Register Bits.
• Lockable 512 byte OTP security sector
• Read Unique ID Number
• Minimum 100K endurance cycle
• Data retention time 20 years
• Package Options
• 8 pins SOP 200mil body width
• 8 contact VDFN(5x6mm)
• 8 pins PDIP
• 16 pins SOP 300mil body width
• 24 balls TFBGA (6x8mm)
• 8 contact VDFN (6x8mm)
• 8 contact USON (4x3x0.55mm)
• All Pb-free packages are compliant RoHS, Halogen-Free and REACH.
• Industrial temperature Range