FEP24C64YSOP8G/TR

The FEP24C64 is an industry-standard EEPROM device that communicates via an industry-standard two-wire interface. The device contains a 64K-bit (8192×8) memory array organized in 32-byte pages. The EEPROM operates over a wide voltage range of 1.7V to 5.5V, making it suitable for most applications. The product offers low-power operation and low standby current. The device is available in lead-free, RoHS-compliant, halogen-free, or green packages. Available package types include 8-pin SOIC, TSSOP, UDFN, MSOP, and SOT23. The FEP24C64 is compatible with standard two-wire bus protocols. This simple bus consists of a serial clock (SCL) signal and a serial data (SDA) signal. Using this bus protocol, a master device (such as a microcontroller) can typically control one or more slave devices, such as this FEP24C64. The bitstream transmitted over the SDA line consists of a series of bytes used to identify a specific slave device, commands, addresses within that slave device, and a series of data (if applicable). The FEP24C64 also provides write protection via the WP pin to prevent overwriting data stored in the memory array. To prevent the state machine from entering an erroneous state during power-up sequences or power-switching conditions, the device incorporates an internal power-on reset circuit. During power-up, the device will not respond to any commands until the supply voltage (VCC) reaches an acceptable stable level above the reset threshold voltage. Once VCC exceeds the power-on reset threshold, the device is reset and enters standby mode. This also prevents any unintended write operations during the power-up phase. During power-down, once VCC falls below the power-on reset threshold voltage, the device enters standby mode. In addition, the device will also enter standby mode after receiving a stop command, provided no internal write operation is in progress. However, issuing commands is not permitted unless VCC is within its valid operating voltage range.

Key features

• Two-wire serial interface, I²C compatible — bidirectional data transfer protocol
• Wide voltage operation
• VCC = 1.7V to 5.5V
• Speed: 1 MHz (1.7V ~ 5.5V)
• Standby current (max): 1 μA, 5.5V
• Read current (max): 0.5 mA, 5.5V
• Write current (max): 0.8 mA, 5.5V
• Hardware data protection
• Write protect pin
• Sequential and random read modes
• Memory organization: 64Kb (8192 × 8)
• Page size: 32 bytes
• Page write mode
• Partial page write supported
• Self-timed write cycle: 5 ms (max)
• Input noise suppression, Schmitt trigger inputs
• High reliability
• Endurance: 1,000,000 cycles
• Data retention: 100 years
• ESD protection >4000 V
• Industrial grade
• Packages: SOIC, TSSOP, UDFN, SOT23, MSOP
• Lead-free, RoHS compliant, halogen-free, green