FT61F135-TRB

Key features

• Only 35 instructions to learn; all instructions are single-cycle (except branch/jump)
• Memory architecture: Program ROM 3k × 14 bits, Data RAM 256 × 8 bits, Data EEPROM 128 × 8 bits
• 8-level hardware stack
• Selectable instruction cycle: 2T/4T
• 125ns @ 2T, 16MHz, VDD ≥ 2.7V
• Operating temperature range: -40°C ~ 85°C
• Wide operating voltage range: 1.9V ~ 5.5V
• Clock sources: Two internal clocks (13.5M/16M high-speed high-accuracy HIRC with software trimming support, 2.5‰ per step; 32k low-speed low-power LIRC); Crystal oscillator and external clock input, crystal clock missing detection, dual-speed clock startup in crystal clock configuration, slow clock cycle measurement
• 16-bit watchdog with 7-bit prescaler, selectable clock source
• Power-on reset delay counter
• Low-power SLEEP mode; system clock can remain active or be disabled
• LVR: 2.0V/2.2V/2.5V/2.8V/3.1V/3.6V/4.1V
• LVD: 1.2V/2.0V/2.4V/2.7V/3.0V/3.3V/3.6V/4.0V or external input voltage
• ISP and OCD support: 3 hardware breakpoints, soft reset, single-step, pause, step-over, etc.
• Program ROM partition protection
• Package options: SOP8, MSOP10, SOP14, SOP16, SOP20, TSSOP20, DIP20
• 18 general-purpose IOs with independently controlled direction: PORTA, PORTB, PORTC
• 8 wake-up pins: PORTA
• 18 pins with open-drain, independently controlled
• 18 pins with pull-up, independently controlled
• 18 pins with pull-down, independently controlled
• ADC input channels: AN0–7
• 8 programmable source-current pins PC0–1, PB2–7: 3/6/24mA @ 5V
• 8 programmable sink-current IOs: max 55mA @ 5V
• Pin alternate function remapping support
• 1 × 12-bit SAR ADC, 8 external channels + 3 internal reference voltage channels (internal reference: VDD, 0.5V, 2V, 3V; external reference: VREFP, VREFN)
• Timer0: 8-bit timer with 8-bit prescaler, selectable clock source
• Timer1: 12-bit timer, selectable clock source
• Timer2: 16-bit timer with 4-bit prescaler and 4-bit postscaler; internal slow clock measurement; 4 independent PWM channels with individually configurable polarity and duty cycle; 1 complementary PWM output pair with dead-band control, mappable to up to 6 IOs; double-buffered duty cycle and period registers; clock sources: HIRC, crystal clock, 2× HIRC, 2× crystal clock, instruction clock, system clock, LIRC; operable in sleep mode; brake input; Buzzer mode; single-pulse mode